A FrontPanel Alloy GUI enables users to generate and view signals with multiple frequency vectors using the SZG-DAC-AD9116 and the SZG-ADC-LTC226x on an XEM8320-AU25P. The FrontPanel Subsystem Vivado IP Core stimulates our HLS Fast Fourier Transform (FFT) cores to combine and convert these vectors into a time domain digital output signal and vice versa. A signal generator only version using an XFP GUI + Lua scripting is also provided.

This sample paired with an Opal Kelly FPGA Development or Integration module provides a great starting template for those interested in DSP applications. The sample can be enhanced by additional DSP processing through additional user defined AMD-Xilinx’s HLS cores, or through AMD-Xilinx’s Filter, Modulation, Trig Functions, etc. DSP IP Cores.

We currently have simpler ADC and DAC example designs available on our open source Github that target the XEM7320 and the XEM8320. Note, these are no longer supported or maintained.

The ADC design is a simple scope that uses Python to display the signals from the ADC. More information is available in the READMEs for the desired XEM module.

The DAC design features AM/FM modulation and can pipe audio into the design to modulate it over a carrier wave with the requested parameters. You can learn more about it on our blog, here.

• GitHub: Opal Kelly’s HLS Fast Fourier Transform (FFT) Core
  A synthesizable and scalable pipelined fixed-point Decimation-in-Frequency FFT and IFFT FPGA library for use with AMD-Xilinx’s High Level Synthesis (HLS).
  
• Github: DAC/ADC Example Design
  A complete sample using HLS FFT and IFFT cores. This sample targets the XEM8320, SZG-DAC-AD9116, and SZG-ADC-LTC226x.
  

Users will be able to:

1. Create IPI Block Designer projects utilizing the FrontPanel Subsystem Vivado IP Core.
2. Use an XFP GUI with FrontPanel Scripting and/or a FrontPanel Alloy GUI for control of FrontPanel-enabled gateware.
3. Get introduced to a workflow that incorporates FrontPanel and AMD-Xilinx’s High Level Synthesis (HLS) components.

• Hardware
  • XEM8320-AU25P
  • SZG-DAC-AD9116 on Port A
  • SZG-ADC-LTC226x on Port B
    • Only required for FrontPanel Alloy Signal Generator + Spectrum Analyzer application
  • Oscilloscope
    • Only required for XFP Signal Generator application
    • Note: For best results, use an oscilloscope with 200 MHz bandwidth to best represent the SZG-DAC-AD9116’s full Nyquist bandwidth of 62.5MHz.
• Pre-built bitfile
  Two bitfiles are provided that correspond to the SZG-ADC-LTC226x
  • DAC-ADC-ExampleDesign-ADC-12-v1.0.bit for the SZG-ADC-LTC2264-12
  • DAC-ADC-ExampleDesign-ADC-14-v1.0.bit for the SZG-ADC-LTC2268-14
• Software
  Two applications are available as options for interfacing with the design
  • FrontPanel Alloy Signal Generator + Spectrum Analyzer
    • DAC-ADC-ExampleDesign-v1.0-AlloyApplication.zip
    • FrontPanel v6.0.0 (alpha) or later
  • XFP Signal Generator
    • FFTSignalGenerator.xfp
    • FFTSignalGenerator.lua
    • FrontPanel 5.2.12 or later

The goal of this tutorial is to use the provided prebuilt bitfile in-hardware to generate a four-tone signal and verify the time and frequency domain characteristics of the signal.

The Signal Generator component of the user interface will be used to configure the IFFT to produce the signal that is output through the SZG-DAC-AD9116. The signal will be routed to the SZG-ADC-LTC226x and the FFT to produce time and frequency domain plots.

1. Power off the XEM8320-AU25P.
2. Connect a SZG-DAC-AD9116 to port A on the XEM8320-AU25P.
3. Connect a SZG-ADC-LTC226x to port B on the XEM8320-AU25P.
4. Connect one of the outputs of the SZG-DAC-AD9116 to one of the inputs of the SZG-ADC-LTC226x.
5. Power on the XEM8320-AU25P using a 12-volt supply.
6. Connect the XEM8320-AU25P to a PC using a USB-C cable.

1. Open FrontPanel 6.0.0 or later.
2. Click the Download FPGA Configuration button.
3. Select the bitfile that corresponds to the SZG-ADC-LTC226x.
   • SZG-ADC-LTC2264-12 requires DAC-ADC-ExampleDesign-ADC-12-v1.0.bit
   • SZG-ADC-LTC2268-14 requires DAC-ADC-ExampleDesign-ADC-14-v1.0.bit
4. Click the Load FrontPanel Profile button.
5. Select the index.html file contained in the DAC-ADC-ExampleDesign-v1.0-AlloyApplication.zip and click the open button.

1. Enable Auto Scaling.
2. Enable the first four frequency vectors.
3. Set the first frequency vector to bin number 199 and -1 dBFS.
4. Set the second fequency vector to bin number 287 and -7 dBFS.
5. Set the third frequency vector to bin number 246 and -28 dBFS.
6. Set the fourth frequency vector to bin number 39 and 0 dBFS.
7. The Time Domain chart should show the waveform of four-tone signal.
8. The Spectrum chart should show the frequency domain representation of the four-tone signal.

The goal of this tutorial is to produce a three-tone wave using the provided prebuilt bitfile in-hardware and capturing the result on an oscilloscope.

1. Power off the XEM8320-AU25P.
2. Connect a SZG-DAC-AD9116 to port A on the XEM8320-AU25P.
3. Power on the XEM8320-AU25P using a 12-volt supply.
4. Connect the XEM8320-AU25P to a PC using a USB-C cable.

1. Connect an oscilloscope probe to either SZG-DAC-AD9116 output’s center pin, and ground the signal on the outer SMA connector, if using a standard probe.
2. Set the oscilloscope to center 0 volts, with a vertical range of +/- ~1 volt.

1. Open FrontPanel 5.2.12 or later.
2. Click the Download FPGA Configuration button.
3. Select the bitfile that corresponds to the SZG-ADC-LTC226x.
   • SZG-ADC-LTC2264-12 requires DAC-ADC-ExampleDesign-ADC-12-v1.0.bit
   • SZG-ADC-LTC2268-14 requires DAC-ADC-ExampleDesign-ADC-14-v1.0.bit
4. Click the Load FrontPanel Profile button and select FFTSignalGenerator.xfp.
   Note: FFTSignalGenerator.lua needs to be in the same directory as FFTSignalGenerator.xfp.

1. Click Reset IFFT.
2. Enable Auto Scaling.
3. Enable bins 1, 2, and 3. Leave bin 4 disabled.
4. Set bin 1 to bin number 1, bin 2 to bin number 2, and bin 3 to bin number 18.
5. Use your mouse’s scroll wheel to set their corresponding dBFS values to -1, -7, and -28.
6. There should now be a three-tone sine wave displaying on the oscilloscope, as shown below.

We provide various build scripts for instructing Vitis HLS to build our FFT core, creating the Vivado project, configuring the required IP Cores, and constructing the IPI Block Design Project. The end result of this How-To is the construction of the following Vivado IPI Block Design project:

This design requires the following to build:

• Vitis HLS
  Notice: Our supported version is v2023.2. Versions outside of this are not guaranteed to be maintained.
• Vivado
  Notice: Our supported version is v2023.2. Versions outside of this are not guaranteed to be maintained.
• Vivado IP Cores’ Distribution v1.0.2 or later
• XEM8320-AU25P Board file v1.2 or later 
• Latest DAC-ADC-ExampleDesign-vX.Y release Source Code (zip or tar.gz)

Windows

1. Follow How-To Install for the XEM8320-AU25P’s Board file v1.2 or later.
2. Follow Add IP Cores’ Distribution to Vivado for Vivado IP Cores’ Distribution v1.0.2 or later. The location you installed this Distribution to will be used in step 6.
3. Extract the sample’s release’s Source Code (zip or tar.gz).
4. Open a command prompt and cd to the DAC-ADC example folder.
   cd C:/pathToDownload/design-resources-DAC-ADC-ExampleDesign-vX.Y/ExampleProjects/DAC-ADC
   Note: PowerShell won’t work, Command Prompt must be used.
5. Run the settings64.bat file in the Vitis HLS and Vivado installation directories.
   path/to/vitis/2023.2/settings64.bat
path/to/vivado/2023.2/settings64.bat
6. Run the appropriate .bat file for your SZG-ADC-LTC226x target:
   – For SZG-ADC-LTC2264-12, use windows_create_project-adc-12.bat.
   – For SZG-ADC-LTC2264-14, use windows_create_project-adc-14.bat.
   Provide the path to the Vivado IP Cores’ Distribution as an argument:
   windows_create_project-adc-12.bat C:/pathToDownload/FrontPanel-Vivado-IP-Dist-vX.Y.Z

Linux

1. Follow How-To Install for the XEM8320-AU25P’s Board file v1.2 or later.
2. Follow Add IP Cores’ Distribution to Vivado for Vivado IP Cores’ Distribution v1.0.2 or later. The location you installed this Distribution to will be used in step 6.
3. Extract the sample’s release’s Source Code (zip or tar.gz).
4. Open a terminal and cd to the DAC-ADC example folder.
   cd C:/pathToDownload/design-resources-DAC-ADC-ExampleDesign-vX.Y/ExampleProjects/DAC-ADC
5. Run the settings64.sh files in the Vitis HLS and Vivado installation directories.
   source path/to/vitis/2023.2/settings64.sh
source path/to/vivado/2023.2/settings64.sh
6. Run the appropriate .bat file for your SZG-ADC-LTC226x target:
   – For SZG-ADC-LTC2264-12, use linux_create_project-adc-12.bat.
   – For SZG-ADC-LTC2264-14, use linux_create_project-adc-14.bat.
   Provide the path to the Vivado IP Cores’ Distribution as an argument:
   linux_create_project-adc-12.bat C:/pathToDownload/FrontPanel-Vivado-IP-Dist-vX.Y.Z

We utilize the Behavioral Simulation features of the FrontPanel Subsystem Vivado IP Core to provide a simulation of the design. The end result of this How-To is the creation of a simulation waveform for a two-tone wave with simulated PipeOut reads of the FFT calculations:

1. Follow How-To Setup the Project
2. In Vivado, launch Flow>Run Simulation>Run Behavioral Simulation
3. Launch Run>Run All

1. Follow How-To Setup the Project
2. In Vivado, launch Flow>Generate Bitfile

• Latest DAC-ADC-ExampleDesign-vX.Y release Source Code (zip or tar.gz)
• Install Prerequisites from Alloy Getting Started Guide

1. Extract the sample’s release’s Source Code (zip or tar.gz).
2. cd to the Alloy folder:
   cd C:/pathToDownload/design-resources-DAC-ADC-ExampleDesign-vX.Y/ExampleProjects/DAC-ADC/Software/Alloy
3. Install the dependencies:
   npm install
4. Build the application:
   npm run build

Below we define terms and three important data flow stages for this sample:

• Frequency Domain BRAM – Contains the 256 frequency domain vectors the FFT computes with.
• IFFT Start – The XFP GUI with FrontPanel Scripting and the FrontPanel Alloy application communicate with the FrontPanel Subsystem Vivado IP Core generated FrontPanel HDL endpoints to store the Vector Set into the Frequency Domain BRAM. A custom RTL Slicer is used to distribute control signals throughout the design.
• FFT Enable – Enables the FFT core to calculate the SZG-ADC input.

The components of this panel are used to control the output of the DAC.

• Add Tone – This appends a new frequency vector component to the list.
• Autoscale – If enabled, will scale the output signal so that it does not exceed the maximum in order to prevent clipping.
• Frequency Vector
  • Bin Slider – This sets the frequency bin number used to configure the IFFT.
  • Frequency (kHz) – The frequency corresponding to the bin number selected.
  • Magnitude (dBFS) – DeciBel Full Scale. 0 = full power, -120 = nearly off.
  • Enabled – If checked, the frequency vector will be included when computing the output signal.
  • X – Removes the frequency vector component from the list.
• Reset – Resets the signal generator components of the design.

The components of these panels are used to retrieve and visualize the input of the ADC.

• Continuous – If enabled, will continuously retrieve frames of 1,024 samples acquired from the ADC.
• Sample – Retrieves a single frame of 1,024 samples acquired from the ADC.
• Reset – Resets the data acquisition components of the design.
• Time Domain Chart – Displays a frame of 1,024 samples retrieved for each of two separate channels.
• Spectrum Chart – Displays the results retrieved from the FFT corresponding to the samples acquired from the ADC.

The user interface shown above has the following components to control the behavior of the FFT signal generator:

• Bin Number – This selects a frequency bin number in the FFT to activate, from 0 to 127.
• dBFS – DeciBel Full Scale. 0 = full power, 120 = nearly off.
  Note: You must use your scroll wheel to input into this entry
• Enable – If unchecked, disables the bin. Also discludes the dBFS value from any Auto Scaling calculations.
• Frequency (kHz) – The frequency of the specified Bin Number.
• Enable Auto Scaling – If enabled, will prevent the sum of all the bin values (calculated from dBFS) from going over the maximum. This will prevent clipping. For example, if two bins were enabled with a dBFS of zero, the Lua script will halve the components to the selected bins and the output signal from the SZG-DAC will not be clipping.
• Reset IFFT – Resets the design.

A limitation of the XFP and FrontPanel Alloy applications provided, is the inablitiy to set the phase of the frequency domain vectors of the Signal Generator. This involves specifying the complex component of the frequency bins. The functionality to do this is present in the gateware, but is not currently implemented in the applications provided with the example.

Our supported releases for the FFT Signal Generator sample are located on GitHub at:
opalkelly-opensource/design-resources Releases

• Renamed design
• Added ADC + IFFT functionality
• FrontPanel Alloy GUI functionality

• Initial Creation
• Bitfile generated using the following tool versions:
  Vivado v2022.1
  Vitis HLS v2022.1
  Vivado IP Cores’ Distribution v1.0.2
  XEM8320-AU25P Board file v1.2