Failure, Repair, and  Warranty Coverage

Unsuitable or unprofessional application and handling are not covered by our warranty. Our products include sensitive electronics and should be handled with care at all times.

Field failure of our products is exceedingly rare under normal operating conditions. In our experience, nearly all failures are due to mishandling, misapplication, or operating out of design specification.

The most common causes of hardware failure are:

  • Over-voltage on a power input  – This can cause permanent damage and cause the board to become non-functional. Due to the possibility of multiple component failure diagnosis and repair is not typically practical.
  • Over-voltage or over-current on a signal line – FPGAs have very high-performance I/O. These devices are not tolerant of voltages out-of-specification and are not designed as high current drivers. Exceeding the device specifications can cause I/O failure or device failure.
  • Touching sensitive components – Many of our devices have high-performance power converters with sensitive feedback networks. Small external influences (such as human touch) can cause these devices to “self-destruct”. It is important not to touch these devices during operation.
  • ESD events – ESD can cause product failure that can be difficult or impractical without extensive (and expensive) root cause analysis. Exercise common sense and professional engineering practices at all times.
  • Hot-plug events – All handling and adjustments must be performed when the device is powered off.

USB Connectivity and Performance

USB connectivity and performance issues are generally related to host software configuration, host hardware configuration, and cabling. Some guidelines and suggestions are listed below.

  • Host port hardware – USB disconnections or performance issues can be related to poor signal integrity. We strongly suggest using a good quality motherboard and ports mounted on the motherboard. Front-panel ports are often attached internally using poor quality cables to headers on the motherboard. These connections and headers degrade signal integrity and can cause problems.
  • Cabling – We have tested a number of commodity USB cables using lab-grade cable testers and found that many are marginal to meeting the USB specification. Poor signal integrity can degrade performance or prevent reliable connections. We do not recommend the use of cable extenders or multi-segment cabling solutions without thorough qualification. Poor performance and/or occasional API timeouts are often symptoms of poor cable solutions.
  • Bad Cables – While we only use a couple qualified cable vendors, a bad cable may sneak through. If you think you may have received a bad cable, please contact and let them know.  We can ship a new cable to you.

Gateware (FPGA and HDL)

Vivado 2020.2 Naming Conflict

Vivado version 2020.2 introduced new behavior that results in a naming conflict and critical warning when using certain Xilinx primitives in a design that includes the FrontPanel HDL. Specifically, use of the Xilinx FIFO Generator IP (and the modules used in that IP) has been found to conflict with modules in use within the FrontPanel HDL. The critical warning that we have seen Vivado throw is:

Overwriting previous definition of module xpm_cdc_async_rst [“**/okCoreHarness.v”:15361]

This or similar critical warnings may present themselves. We are actively working with Xilinx to resolve this issue. Until a viable resolution is reached, the recommendation at this time is to build designs with an earlier version of Vivado.

Through our own internal testing, we have found that ignoring these critical warnings when building and generating designs with Vivado 2020.2 did not have any noticeable effects on the FrontPanel HDL or user HDL. You could alternatively ignore these critical warning while we work to resolve the issue with Xilinx. 

Vivado Encryption Errors

Vivado 2021.1 and later remove support for encryption keys older than five years from the Vivado version used. If you are using FrontPanel HDL sources with expired encryption support, you may encounter the following errors (or similar):

[Synth 8-5809] Error generated from encrypted envelope. ["…/Counters.srcs/okCoreHarness.v":14] [Opt 31-31] Blackbox ep01 (okWireIn) is not supported or not found. This blackbox cannot be found in the existing library. [Opt 31-30] Blackbox ep00 (okWireIn) is driving pin I0 of primitive cell led_OBUFT[0]_inst_i_1. This blackbox cannot be found in the existing library. [Opt 31-236] Found primitives driven by Empty Hierarchy Cells/Black boxes.
Code language: JavaScript (javascript)

If you encounter errors like this, make sure you are using FrontPanel HDL that has been encrypted recent to the version of Vivado you are using. For more information, please visit FrontPanel HDL.