Introduction
The FrontPanel SDK connects host software to an FPGA design. It supplies the host API, the gateware modules, the device firmware, and the application platform that connection requires.
A host-to-FPGA interface requires a physical link, a transfer protocol over that link, firmware at the device end, an endpoint interface inside the FPGA fabric, and a library on the host. The FrontPanel SDK supplies these as matched components for FrontPanel-enabled devices. Figure 1 shows the arrangement, and the boundary between the components the SDK provides and those the user provides.

The sections that follow describe each part and the function it serves.
The Host-to-FPGA Link
FrontPanel establishes and maintains the connection between host software and the FPGA over USB or PCI Express, using the same interface for configuration and for communication.
The SDK provides each layer of that connection: the host driver, the transfer protocol, the endpoint logic in the FPGA, and the host library. These layers are maintained together and revised as operating systems, USB host controllers, and bus generations change.
FrontPanel downloads FPGA configuration files over USB or PCI Express to a target device. Once the bitfile is loaded, the device takes on that design’s personality, and the host interface transitions from a configuration download port to an active communication channel with the running design. Configuration and communication share one connector and one protocol. If configuration is all your application requires, FrontPanel’s role is complete at that point.
Throughput
FrontPanel is built for sustained bulk transfer. The figures below are measured at the API, into an application buffer, rather than the signaling rate of the underlying bus.
| Generation | Host Interface | Controller | data rate |
|---|---|---|---|
| Gen 1 | USB 2.0 High Speed | FX2 | 38 MB/s |
| Gen 2 | USB 3.0 SuperSpeed | FX3 | 340 MB/s |
| Gen 3 | SuperSpeed USB, 10 Gbps | FX10 | 950 MB/s |
| Gen 3 | SuperSpeed USB, 20 Gbps | FX20 | 1400 MB/s |
The table shows representative peak rates by device generation, measured with the PipeTest sample (Gen 1, Gen 2, PCI Express) and the PerfTest sample (Gen 3). Throughput on a given system depends on host hardware, operating system, driver configuration, and transfer sizing. See Performance for measurement conditions, tuning guidance, and per-platform results.
Peripheral Configuration
Opal Kelly modules typically carry peripherals alongside the FPGA: clock generators and PLLs, Flash memory, audio CODECs, SYZYGY ports, EEPROMs, and voltage and sensor control. FrontPanel configures these through the same connection and the same API used to configure the FPGA. PLL outputs are set independently, through the device manager or programmatically. Flash memory is programmed, erased, and reprogrammed through documented calls.
Software Integration
The FrontPanel API is a library your application calls. It presents the device as an ordinary resource: the application opens a device, configures the FPGA, and then reads and writes the interfaces its design exposes — a value to a control register, a block of data to a stream, a status word back. The application works in terms of its own design; the mechanics of the link beneath are handled by the library, the driver, and the device firmware.
The native API is C++, and the library is delivered for Windows, Linux, and macOS. Wrappers ship for Python, C#, Java, and Ruby. The same library loads directly into third-party environments such as MATLAB and LabVIEW, and customers have written wrappers for languages we do not ship.
The Platform API is a second binding, for applications built to run in the FrontPanel Platform. It is a Node.js extension that presents the same C++ API to JavaScript and TypeScript, installed with npm and shipped with TypeScript definitions.
Calls are identical for USB and PCI Express devices. Transport is a property of the device, not of the code written against it. Device discovery and enumeration, FPGA configuration, endpoint access, bulk transfer, sensor readout, and error handling are stable across device generations and host platforms: a new module, a new bus generation, or a new operating system release does not require a corresponding change in the application.
Applications built on the API include image capture, data acquisition, FPGA co-processing, signal generation, instrument control, and production test.
Application Deployment
The FrontPanel Platform is an application runtime for graphical interfaces to FrontPanel devices: bring-up panels, operator screens, demonstrations, and delivered instrument front ends.
Applications are written in TypeScript, HTML, and CSS and run inside a browser runtime with direct access to FrontPanel devices through the Platform API. Rendering, layout, and the component ecosystem come from the web platform; device access comes from the FrontPanel SDK underneath. The Platform is built with Electron, on the same Chromium and Node.js foundation used by popular applications such as Visual Studio Code and Slack.
Nothing about this approach is web-based in the networking sense. Applications are installed and run locally. The runtime is used because it is cross-platform, actively developed, and supported by a large body of libraries, tooling, editor support, and developer knowledge. That same body of knowledge supports AI-assisted development.
The Gateware Interface
Inside the FPGA, the host link terminates at gateware modules you instantiate in your design.
These modules provide control and status register access and bulk data movement, in five forms:
| Form | what it carries | classic | axi |
|---|---|---|---|
| Asynchronous state | Values held in each direction, updated when the host reads or writes them, with no timing relationship to your design’s clocks. | Wires | AXI4-Lite |
| Synchronous events | Single-cycle pulses crossed safely between the host and a clock domain you specify. | Triggers | AXI4-Lite |
| Memory-mapped, single-beat | Addressed register reads and writes — the conventional CSR map. | Register Bridge | AXI4-Lite |
| Memory-mapped, burst | Addressed transfers of many beats per transaction, for memory and memory-like peripherals. | – | AXI4 (Full) |
| Stream | Unidirectional bulk transfer at the rates given above, with optional flow control from the FPGA. | Pipes, BTPipes | AXI4-Stream |
On AXI boards, the first three forms are register patterns on a single AXI4-Lite interface rather than distinct endpoint types. See System Design for the correspondence in full.
Two host interfaces present these forms. FrontPanel Classic HDL is the long-standing interface: an okHost module and a set of endpoint modules sharing a bus. You connect design signals to endpoint ports as you would to external pins. FrontPanel AXI presents standard AXI Manager and Subordinate interfaces on Gen 3 devices, so any AMD or third-party AXI IP connects directly. It carries a built-in operation timeout that bounds every operation and returns partial counts, so a stalled or non-compliant Subordinate cannot hang the host.
Endpoints are added at any point in development by instantiating additional modules. The modules are small, and their effect on a design’s resource budget is minimal. Both interfaces include a behavioral simulation model that mirrors the API calls the host issues on hardware, so a design verified in simulation behaves the same on the board.
Firmware
Between the host software and the gateware is firmware, running on the module’s USB microcontroller or PCI Express bridge device.
The firmware handles enumeration, configuration download, transfer scheduling, peripheral access, device settings storage, and recovery from conditions such as a cable disconnected mid-transfer or a host that aborts an active transaction. It is not written, ported, built, or linked by the user. It ships on the module and is updated through the FrontPanel Platform.
Firmware is versioned separately from the SDK and released independently. Gen 1 firmware has been stable since 2008 and receives no further updates. Gen 2 and Gen 3 firmware are delivered over the internet to the FrontPanel Platform; see FrontPanel Firmware for the version history and Firmware Updates for the update procedure.
Terminology
Collectively, “FrontPanel” names several components. This documentation uses the specific term wherever the distinction matters:
- FrontPanel SDK – The software development kit as a whole: the API, the gateware, the samples, the tools, and this documentation.
- FrontPanel API – The programmer’s interface for custom host applications. Native C++, with wrappers for Python, C#, Java, and Ruby.
- FrontPanel HDL – Gateware modules designed into your FPGA that make it FrontPanel-enabled. Available as Classic HDL and as AXI (
okHost). - FrontPanel Firmware – Firmware on the module’s microcontroller or bridge device providing the conduit between host and FPGA.
- FrontPanel Platform – The application runtime and device manager. Installs and launches Platform Apps and handles device configuration and firmware updates.
- FrontPanel Platform API – The JavaScript / TypeScript API available to applications written for the FrontPanel Platform.
- FrontPanel Classic – The previous native application for Windows, macOS, and Linux, with XML-defined virtual instruments. Superseded by the FrontPanel Platform.
- FrontPanel Driver – The Windows USB driver associated with the device. Linux and macOS require no separate driver.