The Camera example design is an open-source image capture reference built on FrontPanel Platform, pairing AMD Video IP gateware with a browser-based application that auto-detects its hardware. It delivers live streaming, single-frame capture, a hardware-accelerated ISP pipeline (bad pixel correction, demosaicing, auto white balance, gain control), a real-time RGB histogram, a hardware test pattern generator, and client-side YOLO object detection via TensorFlow.js. It supports multiple FPGA board and camera sensor combinations, and runs without a camera attached by falling back to the built-in test pattern generator, providing a foundation for building machine vision applications on Opal Kelly FPGAs.

Host Boards

• XEM8320-AU25P
• SZG-HUB1450-AU10P

SYZYGY Peripherals

• SZG-Camera
• SZG-MIPI-8320
  • Pcam 5C (connects via CAMERA 1)

Links

• Camera Example Design Releases
• FrontPanel Platform Introduction
• Source Code

You’ll need:

• A supported Board / SYZYGY Peripheral combination (see Supported Configurations), or any supported host board alone for TPG-only mode
• FrontPanel Platform 6.x installed (see the FrontPanel Platform Getting Started guide)
• Camera.fpp from the latest Camera Example Design release

To run the example design:

1. Connect the SYZYGY Peripheral to SYZYGY Port A on the host board, connect the board to the PC via USB, and power on. For TPG-only mode, no peripheral is needed.
2. Install the Camera.fpp in the Application Launcher.
3. Drag the Camera app card onto the device card.

• Vivado with Vitis HLS
• FrontPanel Vivado IP Core (for XEM8320-AU25P) or FrontPanel SDK (for SZG-HUB1450-AU10P)
• The latest Camera Example Design release source

Each supported configuration has its own gateware folder under Gateware/<Board>/<Peripheral>/. From that folder:

1. Generate the HLS IP cores (HLS/histogram/, plus HLS/ISP/ if a camera peripheral is included).
2. Run project.tcl in the Vivado TCL console.
3. Generate the bitstream.

See the README in that folder for the exact commands.

• Same development prerequisites as any FrontPanel Platform app (see the Building with NPM Create guide)
• The latest Camera Example Design release source

From the Software/ folder in the release:

npm install
npm run pack

The packaged .fpp is written to Software/output/Camera.fpp. Pre-built bitfiles for all supported configurations ship with the repository, so you do not need to rebuild the gateware first.

Layers. At the top is the React UI: App, CameraView, and the child views for frame, histogram, FPS, and settings. Below it, the orchestration layer runs the capture lifecycle: CapturePipelineSequencer, the three camera controls (SYZYGYCameraControl, PCAMCameraControl, TPGCameraControl), and YoloDetector. Next comes an IP driver layer of thin register wrappers for each pipeline block: ISPDriver, VideoDMADriver, TPGDriver, HistogramDriver, StreamSwitchDriver, I2CController. The drivers call through the AXI abstraction (IAxiLite and IAxiStream) into the FrontPanel Platform API at the bottom.

AXI Interface. IAxiLite and IAxiStream are the seam where everything above becomes board-agnostic. They are implemented twice: once as a thin wrapper over the Platform API’s native AXI data port (HUB1450), and once as a polling bridge over the Classic data port (XEM8320). Every driver, sequencer, and view is written against the interfaces. At startup, the app detects the board and wires up the matching pair. Nothing else in the code has to know which board it’s running on.

Data path. A frame enters at the sensor front-end: a HiSPi deserializer for SZG-Camera or a MIPI CSI-2 RX subsystem for SZG-MIPI-8320. Without a peripheral, there is no front-end and the TPG sources the pipeline directly. In camera configurations the frame passes through the ISP (a Vitis Vision HLS core handling bad pixel correction, gain, demosaicing, and auto white balance) and then the TPG as a passthrough. The VDMA writes the frame into triple-buffered DDR4 and reads it back out to the histogram accelerator, which emits two parallel streams: the passthrough video and a 96-bit histogram. Both feed the stream switch, which picks one, and FrontPanel delivers it to the PC.

Control path. Alongside the video stream, FrontPanel also exposes an AXI-Lite master that drives a control bus to every register-accessible block in the pipeline. On SZG-HUB1450-AU10P, okHost speaks AXI-Lite and AXI-Stream directly. On XEM8320-AU25P, the FrontPanel Vivado IP Core sits behind a small bridge that converts its classic endpoints to AXI.

Release downloads are available on GitHub at: opalkelly-opensource/Camera Releases

Initial Release

A previous version of the Camera Example Design was built on custom RTL gateware paired with a C++/wxWidgets desktop application. It supported a broader set of older FPGA modules (XEM3010, XEM6xxx, XEM7xxx) and the EVB1005/EVB1006 camera boards. That version is archived on the archive/rtl branch of the Camera repository and is provided as-is as a community resource. It is not actively maintained.