The SZG-MIPI-8320 is a breakout board allowing connection of up to three 2-lane MIPI CSI-2 cameras to port A on the XEM8320-AU25P development platform. The IO requirements for this peripheral makes it only compatible with Port A.
XEM8320 Port A Only
HP banks 66 and 67 on the XEM8320-AU25P have their VRP pin connected to ground through a 240 ohm resistor, this is a requirement to use the
MIPI_DPHY_DCI IOSTANDARD. Careful IO planning was done with port A’s connection to bank 66 as well as SZG-MIPI-8320’s connections to port A to ensure that three 2-lane MIPI cameras could be used on this port. IO requirements from PG202 and PG232 were followed as well as ensuring all MIPI lanes are placed onto differential pairs of port A, which are length matched ≤10 mils as per Port A’s SYZYGY compatibility table.
- The CLOCK for MIPI must use a
DBCclock can only be used by data pairs in the same byte group of the bank
QBCclock can be used by any data pair on the same bank
- Highly recommended that the MIPI clock and data pairs be in numerical order, i.e. N0 to N5 of the byte group for one camera. Otherwise additional pin resourced must be used to propagate the signal.
These rules were followed and the following connections established for the SZG-MIPI-8320 paired with port A. Only the P side of the pair is listed. The following information is formatted to directly correspond with the configuration presentation used within Xilinx’s MIPI IPs. You may input the following information directly into the IP wizard to configure the cameras of your choosing.
Three 15 pin FPC connectors that follow the CSI-2 standard are used on the SZG-MIPI-8320. 2-lane MIPI cameras will typically use the 15 pin connector as it will fully populate with 2-lanes. This is in contrast to 22 pin connectors typically seen in 4-lane MIPI cameras. We list camera options below in “Camera Options” that are 2-lane using the 15 pin connector.
Two GPIO are available per camera. GPIO0 (Connector pin 11) is used as a power enable. GPIO1 (Connector pin 12) is multi-use, determined by the camera used.
Because GPIO1 is multi-use, it could either be an input or an output. We provide a direction pin (GPIO1_DIR) connected to the level translators for the GPIO1s to control their direction. Because of the limited IO on port A, GPIO1_DIR controls the direction for all three camera’s GPIO1.
The following is a list of CSI-2 compatible camera modules. They all follow the standard 15 pin FPC connector pinout, but have a variety of uses for the extra GPIO1 pin.
Of the following cameras, we have only tested the SZG-MIPI-8320 with the Digilent PCam 5C. We will be releasing sources for a single and three Pcam port of the Camera Reference Design in the next release.
|Power Enable Setup
|Pi Camera V1.3
2592 × 1944
|Pi Camera V2.1
3280 × 2464
|Pi HQ Camera
4056 x 3040
|Sensor IC GPO pin
|Optional CLK input (0R No Place Jumper)
4656 × 3496
|Programmable focus control
5344 × 4012
|Programmable focus control
Vivado Board File
A companion card board file is available for this SYZYGY peripheral. This companion card board file is only compatible with Port A on the XEM8320-AU25P’s board file.
Version 1.0 is currently provides the following components:
- Two MIPI lane camera module (three total for camera 1-3)
- I2C camera control interfaces (three total for camera 1-3)
- Camera reset (three total for camera 1-3)
Follow the appropriate installation instructions at Vivado Board Files.
- SZG-MIPI-8320 is a Port A only peripheral. You should only add this Companion Card to Port A. Port A’s connection to the I/O bank is able to support 3 two lane MIPI cameras. The other SZG-STD HP bank ports (B and C) do not have this guarantee.
- When the Camera components are placed into the IPI, or connected through the IP Wizard, they will instantiate the MIPI CSI-2 RX Subsystem IP and apply preset configurations for the Diligent Pcam operating at 1080p, 30FPS (420Mbps/Lane). This is the same configuration used in the SZG-MIPI-8320 Camera Reference Design sources. These configurations may be changed as desired.
- SZG-MIPI-8320 will set the VIO to 1.2V to support the MIPI_DPHY_DCI IOSTANDARD. As a result, it is known exactly which voltage will power this bank. When using this Companion Card the IOSTANDARD for the pins connected to this peripheral are set to MIPI_DPHY_DCI for the MIPI connections and LVCMOS12 for the GPIO connections. It is not necessary to constrain these at the top level or through the GUI.
|5V supply required
|Nominal 5V supply current
|Nominal 3.3V supply current
|VIO supply voltage
|Nominal VIO supply current
|Total number of I/O
|Number of differential I/O pairs
|Max 5V Load
|Max 3.3V Load
|Max VIO Load
PIN NUM (J4)lists the pin number on the SYZYGY specification’s Standard Samtec connector, this is reference designator J4 in the schematic.
SIGNAL NAMElists the SYZYGY specification’s name for this pin’s connection.
SCHEMATIC NETlists the net name found in the SZG-MIPI-8320’s schematic for the connection.
|PIN NUM (J4)