SZG-MIPI-8320

The SZG-MIPI-8320 is a breakout board allowing connection of up to three 2-lane MIPI CSI-2 cameras to port A on the XEM8320-AU25P development platform. The IO requirements for this peripheral makes it only compatible with Port A.

Resources 

Design

XEM8320 Port A Only

HP banks 66 and 67 on the XEM8320-AU25P have their VRP pin connected to ground through a 240 ohm resistor, this is a requirement to use the MIPI_DPHY_DCI IOSTANDARD. Careful IO planning was done with port A’s connection to bank 66 as well as SZG-MIPI-8320’s connections to port A to ensure that three 2-lane MIPI cameras could be used on this port. IO requirements from PG202 and PG232 were followed as well as ensuring all MIPI lanes are placed onto differential pairs of port A, which are length matched ≤10 mils as per Port A’s SYZYGY compatibility table.

IO Planning

PG202 and PG232 states the following IO requirements:

  • The CLOCK for MIPI must use a QBC or DBC pair
  • A DBC clock can only be used by data pairs in the same byte group of the bank
  • A QBC clock can be used by any data pair on the same bank
  • Highly recommended that the MIPI clock and data pairs be in numerical order, i.e. N0 to N5 of the byte group for one camera. Otherwise additional pin resourced must be used to propagate the signal.

These rules were followed and the following connections established for the SZG-MIPI-8320 paired with port A. Only the P side of the pair is listed. The following information is formatted to directly correspond with the configuration presentation used within Xilinx’s MIPI IPs. You may input the following information directly into the IP wizard to configure the cameras of your choosing.

NamePin LocPin Name
Clock LaneL18IO_L1P_T0L_N0_DBC_66
Data Lane0M20IO_L2P_T0L_N2_66
Data Lane1J19IO_L3P_T0L_N4_AD15P_66
Camera 1
NamePin LocPin Name
Clock LaneL22IO_L7P_T1L_N0_QBC_AD13P_66
Data Lane0M25IO_L8P_T1L_N2_AD5P_66
Data Lane1K25IO_L9P_T1L_N4_AD12P_66
Camera 2
NamePin LocPin Name
Clock LaneL24IO_L10P_T1U_N6_QBC_AD4P_66
Data Lane0K22IO_L11P_T1U_N8_GC_66
Data Lane1J23IO_L12P_T1U_N10_GC_66
Camera 3

Connector

Three 15 pin FPC connectors that follow the CSI-2 standard are used on the SZG-MIPI-8320. 2-lane MIPI cameras will typically use the 15 pin connector as it will fully populate with 2-lanes. This is in contrast to 22 pin connectors typically seen in 4-lane MIPI cameras. We list camera options below in “Camera Options” that are 2-lane using the 15 pin connector.

GPIO

Two GPIO are available per camera. GPIO0 (Connector pin 11) is used as a power enable. GPIO1 (Connector pin 12) is multi-use, determined by the camera used.

Because GPIO1 is multi-use, it could either be an input or an output. We provide a direction pin (GPIO1_DIR) connected to the level translators for the GPIO1s to control their direction. Because of the limited IO on port A, GPIO1_DIR controls the direction for all three camera’s GPIO1.

Camera Options

The following is a list of CSI-2 compatible camera modules. They all follow the standard 15 pin FPC connector pinout, but have a variety of uses for the extra GPIO1 pin.

Of the following cameras, we have only tested the SZG-MIPI-8320 with the Digilent PCam 5C. We will be releasing sources for a single and three Pcam port of the Camera Reference Design in the next release.

Model NumberManufacturerSensorResolutionPower UsagePower Enable Setup
(GPIO0)
GPIO1Features
Pi Camera V1.3Raspberry PiOmniVision OV56475MP
2592 × 1944
200-250mA LED Indicator 
Pi Camera V2.1Raspberry PiSony IMX2198MP
3280 × 2464
200-250mALDO EnableNC 
Pi HQ CameraRaspberry PiSony IMX47712.3MP
4056 x 3040
200-250mARegulator EnableSensor IC GPO pin 
PCam 5CDigilentOV5640-A71A5MP200mALDO EnableOptional CLK input (0R No Place Jumper)M12 Lens
Pivariety 16MPArducamIMX29816MP
4656 × 3496
UnknownUnknownUnknownProgrammable focus control
Pivariety 21MPArducamIMX23021MP
5344 × 4012
UnknownUnknownUnknownProgrammable focus control

Vivado Board File

A companion card board file is available for this SYZYGY peripheral. You can make a “board connection” with this companion card board file and your XEM8320-AU25P’s board file to utilize the components within the IPI block designer. This companion card board file is only compatible with STD ports on the XEM8320-AU25P’s board file.

Version 1.0 is currently available in Vivado version 2021.1 and later and provides the following components:

  • Two MIPI lane camera module (three total for camera 1-3)
  • I2C camera control interfaces (three total for camera 1-3)
  • Camera reset (three total for camera 1-3)

How-To Install

  1. Create a new project
  2. In the “Default Part” menu, select the “Boards” tab
  3. Fetch the latest available boards/versions from Xilinx’s Board Store Git repository by clicking the “Refresh” button
  4. Use the Vendor filter and select “opalkelly.com”
  5. Install the “SZG_MIPI_8320 Peripheral” board file by clicking the install icon in the “Status” column of the board listing
  6. Add this connection to the XEM8320-AU25P’s board file by selecting “Add Companion Card”

Notes

  • SZG-MIPI-8320 is a Port A only peripheral. You should only add this Companion Card to Port A. Port A’s connection to the I/O bank is able to support 3 two lane MIPI cameras. The other SZG-STD HP bank ports (B and C) do not have this guarantee.
  • When the Camera components are placed into the IPI, or connected through the IP Wizard, they will instantiate the MIPI CSI-2 RX Subsystem IP and apply preset configurations for the Diligent Pcam operating at 1080p, 30FPS (420Mbps/Lane). This is the same configuration used in the SZG-MIPI-8320 Camera Reference Design sources. These configurations may be changed as desired.
  • SZG-MIPI-8320 will set the VIO to 1.2V to support the MIPI_DPHY_DCI IOSTANDARD. As a result, it is known exactly which voltage will power this bank. When using this Companion Card the IOSTANDARD for the pins connected to this peripheral are set to MIPI_DPHY_DCI for the MIPI connections and LVCMOS12 for the GPIO connections. It is not necessary to constrain these at the top level or through the GUI.

SYZYGY Information

Compatibility Table

COMPATIBILITY PARAMETER SPECIFICATION
Port typeSYZYGY Standard
WidthSingle
5V supply requiredNo
Nominal 5V supply currentN/A
Nominal 3.3V supply current750mA
VIO supply voltage1.2V
Nominal VIO supply currentN/A
Total number of I/O13
Number of differential I/O pairs18

DNA Data

DNA PARAMETER DATA
Max 5V Load0mA
Max 3.3V Load1000mA
Max VIO Load10mA
IS_LVDSFalse
IS_DOUBLEWIDEFalse
IS_TXR4False
VIO Range(s)[1.2,1.2]

Pinout

The source of the following pinout information is the SZG-MIPI-8320 schematic. This pinout follows the SYZYGY specification for STD ports.

  • Column PIN NUM (J4) lists the pin number on the SYZYGY specification’s Standard Samtec connector, this is reference designator J4 in the schematic.
  • Column SIGNAL NAME lists the SYZYGY specification’s name for this pin’s connection.
  • Column SCHEMATIC NET lists the net name found in the SZG-MIPI-8320’s schematic for the connection.
PIN NUM (J4)SIGNAL NAME SCHEMATIC NET
5D0PCAM1_CLK_P
7D0NCAM1_CLK_N
9D2PCAM1_LANE0_P
11D2NCAM1_LANE0_N
13D4PCAM1_LANE1_P
15D4NCAM1_LANE1_N
22S17CAM1_SCL_VIO
24S19CAM1_SDA_VIO
21S16CAM1_GPIO0_VIO
23S18CAM1_GPIO1_VIO
17D6PCAM2_CLK_P
19D6NCAM2_CLK_N
6D1PCAM2_LANE0_P
8D1NCAM2_LANE0_N
14D5PCAM2_LANE1_P
16D5NCAM2_LANE1_N
26S21CAM2_SCL_VIO
28S23CAM2_SDA_VIO
25S20CAM2_GPIO0_VIO
27S22CAM2_GPIO1_VIO
10D3PCAM3_CLK_P
12D3NCAM3_CLK_N
18D7PCAM3_LANE0_P
20D7NCAM3_LANE0_N
33P2C_CLKpCAM3_LANE1_P
35P2C_CLKnCAM3_LANE1_N
30S25CAM3_SCL_VIO
32S27CAM3_SDA_VIO
29S24CAM3_GPIO0_VIO
31S26CAM3_GPIO1_VIO
34C2P_CLKpGPIO1_DIR