The SZG-ENET1G is a 10/100/1000 Mb/s RGMII Ethernet PHY module featuring the Texas Instruments DP83867IRPAP PHY. This module is an excellent choice for adding Ethernet connectivity to your SYZYGY carrier board. Connection to the PHY through the RJ-45 cage allows standard Ethernet cable to be used.

Resources 

Design

Strapping

The TI DP83867IRPAP PHY’s default configuration is determined by “Strapping” resistors placed onto targeted pins of the PHY. We have provided strapping resistor locations onto the PCB for some pins which are mentioned below. You can read how to strap these pins in the DP83867 datasheet. Other pins have not been given strapping locations on the PCB and the resulting default behavior is specified below. The operating state may be changed from the default state post power-up/reset using the MDIO configuration interface.

RGMII Strapping

Pin RX_D6 on the PHY has been strapped for mode 0, which is RGMII only operation. This is the only mode supported by the SZG-ENET1G as only 4 RX and 4 TX lanes can be routed to the SYZYGY STD connector’s differential pairs, which are usually length matched ≤10 mils. Specific length matching numbers for the differential pairs are specified by your carrier product’s SYZYGY port Compatibility Tables. Strapping resistor locations are not provided on the PCB for this pin on the PHY.

Auto-Negotiation Strapping

Pin RX_DV/RX_CTRL on the PHY has been strapped to enable auto-negotiation. Pin LED_1 and RX_D4 are strapped to advertise an ability for 10/100/1000 during auto-negotiation. Strapping resistor locations are only provided for the RX_DV/RX_CTRL pin on the PHY.

RX/TX Delay Strapping

The PAP variant of the DP83867 PHY does not support the RGMII TX and RX DLL Skew straps. As a result, by default there is no delay/skew applied to the RX or TX paths.

Address Strapping

Strapping resistor locations have been added to pins RXD0, RXD2, and RXD4 on the PCB for specifying the address of the PHY when using the Serial Management Interface. These resistors are not populated, giving the device an address of 0x00.

Clock Strapping

Strapping resistor locations have been added to pin RXD7. These resistors are not populated, enabling the clock output. By default this clock output is synchronous to the XI oscillator / crystal input and is outputted to the CLK_OUT pin. 

TX_CLK and RX_CLK

The TX_CLK net (GTX_CLK pin on PHY) is sourced from the MAC and provided to the PHY. The RX_CLK net provides the recovered received clock during operation. From the DP83867 datasheet: “For Gigabit operation the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and 100-Mbps operation, the clock frequencies are 2.5 MHz and 25 MHz, respectively.”

Ethernet MAC ID PROM

This is an EEPROM device Pre-Programmed with a EUI-48™ MAC Address that has been assigned by the IEEE Registration Authority. It is accessed via I2C at the 7 bit address 0x57. The most significant byte for the 48 bit MAC address is at address 0xFA and the least significant byte is at address 0xFF. You can read more about this in the 24AA025E48’s datasheet. 

RJ-45 Cage LEDs

The RJ-45 cage used has three LEDs whose on/off states are controlled by the LED_0, LED_1, and LED_2 pins from the PHY. Green and orange LEDs are on the left hand side of the cage which will combine to show brown if both are luminated. A yellow LED is on the right hand side of the cage. The following connections and default behavior are as follows:

  • Yellow (LED_2) on right side of cage: RX/TX Activity
  • Orange (LED_1) on left side of cage: 1000 Link Up
  • Green (LED_0) on left side of cage:    Any Link Up

Vivado Board File

A companion card board file is available for this SYZYGY peripheral. You can make a “board connection” with this companion card board file and your SYZYGY carrier board’s board file to utilize the components within the IPI block designer. This companion card board file is only compatible with STD ports on the SYZYGY carrier board’s board file.

Version 1.0 is currently available in Vivado version 2021.1 and later and provides the following components:

  • I2C ethernet MAC address EEPROM (assigned by the IEEE registration authority)
  • PHY reset
  • RGMII interface to on-board PHY

How-To Install

  1. Create a new project
  2. In the “Default Part” menu, select the “Boards” tab
  3. Fetch the latest available boards/versions from Xilinx’s Board Store Git repository by clicking the “Refresh” button
  4. Use the Vendor filter and select “opalkelly.com”
  5. Install the “SZG_ENET1G Peripheral” board file by clicking the install icon in the “Status” column of the board listing
  6. Add this connection to your SYZYGY carrier board’s board file by selecting “Add Companion Card”

Notes

  • The on-board PHY component is only supported in Vivado 2021.1.1 at this time.

SYZYGY Information

Compatibility Table

COMPATIBILITY PARAMETER SPECIFICATION
Port typeSYZYGY Standard
WidthSingle
5V supply requiredNo
Nominal 5V supply currentN/A
Nominal 3.3V supply current150mA
VIO supply voltage1.8V, 2.5V or 3.3V
Nominal VIO supply current35mA
Total number of I/O16
Number of differential I/O pairs0

DNA Data

DNA PARAMETER DATA
Max 5V Load0mA
Max 3.3V Load150mA
Max VIO Load35mA
IS_LVDSFalse
IS_DOUBLEWIDEFalse
IS_TXR4False
VIO Range(s)[1.8,1.8], [2.5,2.5], [3.3,3.3]

Pinout

The source of the following pinout information is the SZG-ENET1G schematic. This pinout follows the SYZYGY specification for STD ports.

  • Column PIN NUM (J1) lists the pin number on the SYZYGY specification’s Standard Samtec connector, this is reference designator J1 in the schematic.
  • Column SIGNAL NAME lists the SYZYGY specification’s name for this pin’s connection.
  • Column SCHEMATIC NET lists the net name found in the SZG-ENET1G’s schematic for the connection.
PIN NUM (J1)SIGNAL NAME SCHEMATIC NET
5D0PRX_CTL
7D0NTX_CTL
6D1PRESET_ENET_N
8D1NINT_N
9D2PRXD3
11D2NRXD2
10D3PTXD0
12D3NTXD1
13D4PRXD1
15D4NRXD0
14D5PTXD2
16D5NTXD3
17D6PEEPROM_SCL
19D6NEEPROM_SDA
18D7PMDC
20D7NMDIO
33P2C_CLKpRX_CLK
34C2P_CLKpTX_CLK