The SZG-ADC-LTC2264 is a 2-channel, 12-bit, 40 MSPS ADC based on the Analog Devices LTC2264-12 ADC. The converter module is perfect for high-performance communications applications and general high-speed data acquisition.
The module is configured to accept a conversion clock from the FPGA on the carrier or (with user-applied resistor changes) a single-ended clock delivered by an on-board SMA connector.
|Port type||SYZYGY Standard|
|5V supply required||No|
|Nominal 5V supply current||0mA|
|Nominal 3.3V supply current||500mA|
|VIO supply voltage||1.2V to 3.3V|
|Nominal VIO supply current||< 10mA|
|Total number of I/O||15|
|Number of differential I/O pairs||5|
This data is stored in the SYZYGY DNA microcontroller on the SZG-ADC-LTC226X peripheral.
|Max 5V Load||0 mA|
|Max 3.3V Load||500 mA|
|Max VIO Load||10 mA|
PIN NUM (J1)lists the pin number on the SYZYGY specification’s Standard Samtec connector, this is reference designator J1 in the schematic.
SIGNAL NAMElists the SYZYGY specification’s name for this pin’s connection.
SCHEMATIC NETlists the net name found in the SZG-ADC-LTC226X’s schematic for the connection.
|PIN NUM (J1)||SIGNAL NAME||SCHEMATIC NET|
The design of the SZG-ADC-LT226X has been heavily influenced by the evaluation board designed and produced by Linear Technology (Analog Devices).
Linear Technology (Analog Devices) LTC2262
From the LTC226X datasheet:
The LTC®2265-12/LTC2264-12/LTC2263-12 are 2-channel, simultaneous sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 71 dB SNR and 90 dB spurious free dynamic range (SFDR). Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance.
DC specs include ±0.3 LSB INL (typ), ±0.1 LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.3 LSB RMS.
The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity.
ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
The applicable input frequency range of the SZG-ADC-LTC226X is approximately 5 MHz to 140 MHz. For optimal distortion and noise performance, or for input frequencies above 140 MHz, the RC networks on the analog inputs may need to be optimized. For optimal SNR performance, external filters may be required. Refer to the documentation below.
|Maximum analog input voltage||2 Vpp*|
|Input impedance||50 Ω|
* The input range may be adjusted using the
SENSE pin on the LTC226x. Refer to the documentation below.
Encode Clock Input
By default, the SZG-ADC is configured to accept a differential clock over the
C2P_CLK connection from the carrier. To apply an external single-ended clock over the SMA connector J4, remove resistors R18 and R28, and place resistors R20 and R27.
The encode clock inputs may be driven at any level up to 3.6 V. When driving the inputs using a differential signal, the negative input (
ENC-) must stay at least 200 mV above circuit ground.
PCB Revision History
|SZG-ADC-LTC226X||DXX||Current production PCB.|
SDO Level Translator Incompatibility
SDO connection in the SPI configuration interface is incompatible with the level translator. This means that the ADC’s configuration registers can be written to, but not read. Register read is only used to verify the written configuration, as there are no status or data registers available from that interface. A fix will be implemented in the next revision.