The DUALSFP peripheral provides a pair of SFP+ sockets to a SYZYGY Transceiver port for use with high-performance serial standards over optical or copper wire connections.

The SZG-DUALSFP peripheral is a TXR device and not compatible with TXR4 carrier ports.

Resources

SYZYGY Information

Compatibility Table

COMPATIBILITY PARAMETERSPECIFICATION
Port typeSYZYGY Transceiver
WidthSingle
5V supply requiredNo
Nominal 5V supply currentN/A
Nominal 3.3V supply current360 mA (based on 2x Finisar FTLF8524P2BNV modules)
VIO supply voltage3.3V
Nominal VIO supply current< 100mA
Total number of I/O14

DNA Data

This data is stored in the SYZYGY DNA microcontroller on the SZG-DUALSFP peripheral.

Note that the maximum 3.3V load below is an overestimate due to the variability in power consumption between SFP modules.

DNA PARAMETERDATA
Max 5V Load0 mA
Max 3.3V Load2000 mA
Max VIO Load10 mA
IS_LVDSFalse
IS_DOUBLEWIDEFalse
VIO Min3.3V
VIO Max3.3V

Pinout

The source of the following pinout information is the SZG-DUALSFP schematic. This pinout follows the SYZYGY specification for TXR2 ports.

  • Column PIN NUM (J1) lists the pin number on the SYZYGY specification’s Transceiver Samtec connector, this is reference designator J1 in the schematic.
  • Column SIGNAL NAME lists the SYZYGY specification’s name for this pin’s connection.
  • Column SCHEMATIC NET lists the net name found in the SZG-DUALSFP’s schematic for the connection.
PIN NUM (J1)SIGNAL NAMESCHEMATIC NETNOTE
5RX0pSFP1_RDP
7RX0nSFP1_RDN
6TX0pSFP1_TDP
8TX0nSFP1_TDN
9 RX1pSFP2_RDP
11RX1nSFP2_RDN
10TX1pSFP2_TDP
12TX1nSFP2_TDN
13REFCLKpREFCLKP125 MHz LVDS clock 
15REFCLKnREFCLKN125 MHz LVDS clock 
14S0SFP1_MOD_DEF2
16S1SFP1_RATE_SELECT
17S2SFP1_TFAULT
18S3SFP2_TDIS
19S4SFP1_TDIS
20S5SFP2_MOD_DEF2
21S6SFP1_MOD_DEF1
22S7SFP2_MOD_DEF1
23S8SFP1_MOD_DEF0
24S9SFP2_MOD_DEF0
25S10SFP1_LOS
26S11SFP2_RATE_SELECT
27S12SFP2_TFAULT
28S13SFP2_LOS

Design

The DUALSFP peripheral provides a pair of SFP+ sockets to a SYZYGY Transceiver port for use with high-performance serial standards over optical or copper wire connections.

Primary Components

COMPONENTMANUFACTURERMANUFACTURER P/N
Dual SFP CageAmphenolU77-A2114-200T
SFP ReceptacleAmphenolUE75-A20-6000T

Tested SFP Modules

MANUFACTURERMANUFACTURER P/NCOMMENT
FinisarFTLF8524P2BNV4.25 Gb/s Short-Wavelength SFP Transceiver

Eye Diagrams

Several eye diagrams were taken using Xilinx’s iBERT tool to empirically test the quality of the link.

Test conditions and setup:

  • Vivado 2017.2
  • iBERT version 3.0 (Rev. 15)
  • Brain-1 used as the carrier
  • Peripheral contained two Finisar FTL8524P2BNV SFP transceivers
  • Scans performed at 3.75Gbps

Scan 0 (SFP1 Position – Direct SYZYGY)

Scan 1 (SFP2 Position – Direct SYZYGY)