The SZG-PMOD4 is a SYZYGY Standard module that provides expansion to up to four Digilent Pmod peripherals.

• Aligni PLM – See the Attachments tab for schematics and Altium Designer project files.
• SYZYGY Specification

This data is stored in the SYZYGY DNA microcontroller on the SZG-PMOD peripheral.

Note that the maximum 3.3V load below is an overestimate to account for the potential variability in current loads between Pmod modules.

The PMOD4 peripheral is a basic device that breaks out a single SYZYGY Standard port into up to 4 Digilent Pmod connectors.

Each signal is routed through a 200Ω series resistor before connecting to its corresponding SYZYGY connector pin. This is to reduce current in the case of a shorted connection to avoid damage to the FPGA I/O.

Additionally, each signal is routed through an ESD protection diode (ON Semiconductor NSQA6V8AW5T2G) on the Pmod side of the series resistor.

SZG-PMOD4 boards with PCB date code 20170719 are designed such that the 3.3V rail powers all Pmod peripherals connected to the SZG-PMOD4. It is possible for Pmod peripherals to back power the VIO rail through FPGA I/O internal clamp diodes under the following conditions:

• +3.3V power is enabled while +VIO is disabled. The SYZYGY specification calls for +3.3V to turn on first. The carrier implementation and peripheral configuration determines how long this condition lasts. It could be short (10’s of milliseconds) or it could be indefinite (if VIO is never enabled).
• The peripheral drives (applies) a voltage onto the I/O pins.

The scope of the issue depends on the specific carrier and peripherals in an application. Damage can occur to the FPGA is the back current applied to the pin exceeds 10mA. On the Opal Kelly XEM7320, there are no other significant power users attached to the VIO and no VIO is shared among peripherals. Therefore, no significant current would pass through the clamp diodes. On the Opal Kelly Brain-1, a second peripheral on the same VIO bank could draw current and force this current through the clamp diodes. Other carrier designs may also experience damage if their VIO power supply design is capable of sinking current prior to the VIO rail powering on.

A revised design to resolve this issue is in progress. At this time, we do not feel that this presents a significant risk of damage for most system configurations.

If you have any questions or comments, please feel free to reach out to Opal Kelly Support.