The SZG-DISPLAYPORT is a dual DisplayPort 1.4 capable module with one source and one sink port. It features a Texas Instruments SN65DP141RLJ re-driver on the source port, and a Kinetic Technologies MCDP6000C1 re-timer on the sink port. This module is an excellent choice for development of DisplayPort input, output, or performing real-time analysis, processing, or editing of pass-through video.

• Aligni PLM – See the Attachments tab for schematics.
• SYZYGY Specification
• SYZYGY GitHub Site – Several projects that could be helpful.

The DisplayPort source port uses all 4 of the SYZYGY TXR4 ports transceiver TX lanes, while the sink port uses all 4 of the RX lanes. The source and sink ports utilizes a redriver and a retimer, respectively.

The module includes two full size DisplayPort connectors. Providing both a DisplayPort source and sink.

The onboard 270 MHz reference clock provides the clock source required for DisplayPort 1.4 operation.

See Xilinx document PG230 table 75 and 76 for refclock requirements at different line rates.

The source of the following pinout information is the SZG-DISPLAYPORT schematic. This pinout follows the SYZYGY specification for TXR4 ports.

• Column PIN NUM (J1) lists the pin number on the SYZYGY specification’s Standard Samtec connector, this is reference designator J1 in the schematic.
• Column SIGNAL NAME lists the SYZYGY specification’s name for this pin’s connection.
• Column SCHEMATIC NET lists the net name found in the SZG-DISPLAYPORT’s schematic for the connection.