SZG-TST-TXR4
The SZG-TST-TXR4 is a SYZYGY Transceiver peripheral intended to be used by SYZYGY carrier developers to test continuity during development or production of their carrier. It can be used during automated testing to validate connector I/O.
Resources
- Aligni PLM – See the Attachments tab for schematics.
- SYZYGY Specification
SYZYGY Information
Compatibility Table
| COMPATIBILITY PARAMETER | SPECIFICATION |
|---|---|
| Port type | SYZYGY Transceiver |
| Width | Single |
| 5V supply required | Yes |
| Nominal 5V supply current | < 10mA |
| Nominal 3.3V supply current | < 10mA |
| VIO supply voltage | 1.8V |
| Nominal VIO supply current | < 100mA |
| Total number of I/O | Up to 18 |
DNA Data
This data is stored in the SYZYGY DNA microcontroller on the SZG-TST-TXR4 peripheral.
| DNA PARAMETER | DATA |
|---|---|
| Max 5V Load | 10 mA |
| Max 3.3V Load | 10 mA |
| Max VIO Load | 10 mA |
| IS_LVDS | False |
| IS_DOUBLEWIDE | False |
| IS_TXR4 | True |
| VIO Min | 1.8V |
| VIO Max | 1.8V |
Pinout
The source of the following pinout information is the SZG-TST-TXR4 schematic. This pinout follows the SYZYGY specification for TXR4 ports.
- Column
PIN NUM (J1)lists the pin number on the SYZYGY specification’s Transceiver Samtec connector, this is reference designator J1 in the schematic. For connections that are looped back, both pins are listed. - Column
SIGNAL NAMElists the SYZYGY specification’s name for this pin’s connection. For connections that are looped back, both signal names are listed. - Column
SCHEMATIC NETlists the net name found in the SZG-TST-TXR4’s schematic for the connection.
| PIN NUM (J1) | SIGNAL NAME | SCHEMATIC NET | NOTE |
|---|---|---|---|
| 5 <-> 6 | RX0p <-> TX0p | LOOPBACK_0P | 0.01 μF AC-coupling capacitor |
| 7 <-> 8 | RX0n <-> TX0n | LOOPBACK_0N | 0.01 μF AC-coupling capacitor |
| 9 <-> 10 | RX1p <-> TX1p | LOOPBACK_1P | 0.01 μF AC-coupling capacitor |
| 11 <-> 12 | RX1n <-> TX1n | LOOPBACK_1N | 0.01 μF AC-coupling capacitor |
| 13 | REFCLKp | REFCLKP | 125 MHz reference oscillator |
| 14 | S0 | TEST_MODE_3_VIO (Atmel PB0, U1 pin 11) | |
| 15 | REFCLKn | REFCLKN | 125 MHz reference oscillator |
| 16 | S1 | TEST_MODE_2_VIO (Atmel PB1, U1 pin 12) | |
| 17 | S2 | TEST_MODE_1_VIO (Atmel PB2, U1 pin 14) | |
| 18 | S3 | TEST_MODE_0_VIO (Atmel PA7, U1 pin 15) | |
| 19 <-> 20 | S4 <-> S5 | S5_S4_LOOP | |
| 21 <-> 22 | S6 <-> S7 | S6_S7_LOOP | |
| 23 <-> 24 | S8 <-> S9 | S8_S9_LOOP | |
| 25 <-> 26 | RX3p <-> TX3p | LOOPBACK_3P | 0.01 μF AC-coupling capacitor |
| 27 <-> 28 | RX3n <-> TX3n | LOOPBACK_3N | 0.01 μF AC-coupling capacitor |
| 29 <-> 30 | RX2p <-> TX2p | LOOPBACK_2P | 0.01 μF AC-coupling capacitor |
| 31 <-> 32 | RX2n <-> TX2n | LOOPBACK_2N | 0.01 μF AC-coupling capacitor |
| 33 <-> 34 | P2C_CLKp <-> C2P_CLKp | LOOPBACK_CLKP | |
| 35 <-> 36 | P2C_CLKn <-> C2P_CLKn | LOOPBACK_CLKN |
Design
The SZG-TST-TXR4 is designed to assist carrier developers perform continuity and power supply tests during development and production testing. To accomplish this, the test peripheral connects a communication path from the FPGA to the Atmel MCU for power supply tests. The remaining pins on the connector are shorted together according to the connections in the table above to allow for continuity testing.
Test Firmware
The Atmel MCU on the test peripherals contains a modified version of the normal DNA firmware. The test firmware removes the power supply sequencing options present in the standard firmware.The test firmware also uses the AVR to measure each of the power supply rails, reporting their status back to the FPGA.
Each supply rail is measured with the internal AVR ADC and checked against a pair of threshold values corresponding to the SYZYGY specified tolerance of that power supply rail. If the supply rail is within its required tolerance the AVR sets a “good” status bit for that rail. The VIO rail is assumed to be at 1.8V by the AVR firmware and the DNA for the test peripheral. A 1.8V VIO is used to maximize compatibility with current FPGA I/O supply requirements.
Supply status is communicated back to the FPGA through SYZYGY pins 14, 16, 17, and 18. The AVR continuously reads AVR pin PA7 (SYZYGY Pin 18 (S3)), then outputs the power supply state on the PB[2:0] pins according to the table below.
| +5V Supply | +3.3V Supply | VIO Supply | ||
|---|---|---|---|---|
| PA7 = 1 | Good | PB0 = 1 | PB2 = 1 | PB1 = 1 |
| Bad | PB0 = 0 | PB2 = 0 | PB1 = 0 | |
| PA7 = 0 | Good | PB0 = 0 | PB2 = 0 | PB1 = 0 |
| Bad | PB0 = 1 | PB2 = 1 | PB1 = 1 |
By toggling the PA7 pin with the FPGA it is possible to test continuity on the MCU pins while also checking the status of each power supply.