The SZG-PCIEX4 routes the PCIe connector pinout to the SYZYGY Samtec connector. This module is an excellent choice for adding PCIe connectivity to your SYZYGY carrier board. The provided Samtec cable is used to connect the SZG-PCIEX4 to your host PC.

Resources 

Design

x4 or x1 Lane Configuration

TXR4 SYZYGY ports contain 4 RX/TX lanes connected to a transceiver quad of the FPGA. TXR2 ports only contain 2. The SZG-PCIEX4, by default, is a TXR4 (4-lane) peripheral and is compatible with the TXR4 carriers such as the XEM8320, BRK8350, and BRK1900. To use with TXR2 carriers such as the XEM7320 and SZG-BRAIN1, the following modifications to the SZG-PCIE4 PCB are required:

  • Remove resistor R15
  • Place the removed resistor onto R14

This indicates to the host PC that this connection is x1 lane instead of x4 lanes. The PCIe connector pinout only allows for x1, x4, x8, and x16 lane configurations. As a result only PCIe X1 is supported on the XEM7320 and Brain-1. You can read more about the PRSNT pin in the PCI Express specification. 

Restrictions

Samtec Cable Length

Through our own internal testing we were able to establish and exercise PCIe Gen 3 x4 Lane links up to 8 feet in cable length. Cable lengths beyond this will either fail to enumerate or train down.

SYZYGY Information

Compatibility Table

COMPATIBILITY PARAMETER SPECIFICATION
Port typeSYZYGY TXR4 (Default)
SYZYGY TXR2 (With Modification)
WidthSingle
5V supply requiredNo
Nominal 5V supply currentN/A
Nominal 3.3V supply currentN/A
VIO supply voltage1.2V-2.5V, 3.3V
Nominal VIO supply currentN/A
Total number of I/O4
Number of differential I/O pairs9

DNA Data

DNA PARAMETER DATA
Max 5V Load0mA
Max 3.3V Load10mA
Max VIO Load10mA
IS_LVDSTrue
IS_DOUBLEWIDEFalse
IS_TXR4True
VIO Range(s)[1.2,2.5], [3.3,3.3]

Pinout

SYZYGY (J1)CONNECTION
5 (RX0p)PCIE_RX0P
7 (RX0n)PCIE_RX0N
6 (TX0p)PCIE_TX0P
8 (TX0n)PCIE_TX0N
9 (RX1p)PCIE_RX1P
11 (RX1n)PCIE_RX1N
10 (TX1p)PCIE_TX1P
12 (TX1n)PCIE_TX1N
13 (REFCLKp)PCIE_REFCLKP
15 (REFCLKn)PCIE_REFCLKN
14 (S0)PCIE_SMCLK_VIO
16 (S1)PCIE_SMDAT_VIO
17 (S2)PCIE_PERST_B_VIO
19 (S4)Not Connected
18 (S3)PCIE_WAKE_B_VIO
20 (S5)Not Connected
21 (S6)Not Connected
22 (S7)Not Connected
23 (S8)Not Connected
24 (S9)Not Connected
25 (RX3p)PCIE_RX3P
27 (RX3n)PCIE_RX3N
26 (TX3p)PCIE_TX3P
28 (TX3n)PCIE_TX3N
29 (RX2p)PCIE_RX2P
31 (RX2n)PCIE_RX2N
30 (TX2p)PCIE_TX2P
32 (TX2n)PCIE_TX2N
33 (P2C_CLKp)Not Connected
35 (P2C_CLKn)Not Connected
34 (C2P_CLKp)Not Connected
36 (C2P_CLKn)Not Connected