The SZG-QSFP allows connecting a QSFP+ module to an FPGA transceiver bank via the SYZYGY TXR4 port. All of the QSFP+ module control signals are connected to IO and have level shifting on board to allow for a variety of compatible bank voltages.
An on board 156.25Mhz oscillator is provided as a transceiver reference clock. This frequency is compatible with a variety of Ethernet protocols.
SYZYGY Port Pin
Control I/O Tri-State
Normally the QSFP control signals are tri-stated (high impedance) whenever either 3.3V or VIO is down. However this function can be manually controlled via an I/O pin, if required. To do so remove R5 and place R7 and R8.
Column PIN NUM (J1) lists the pin number on the SYZYGY specification’s Standard Samtec connector, this is reference designator J1 in the schematic.
Column SIGNAL NAME lists the SYZYGY specification’s name for this pin’s connection.
Column SCHEMATIC NET lists the net name found in the SZG-QSFP’s schematic for the connection.
PIN NUM (J1)
156.25Mhz LVDS Clock
156.25Mhz LVDS Clock
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