Ethernet Reference Design

Note on Carrier Compatibility

We provide gateware for the XEM8320 as an example. Applying the Xilinx example design to other compatible carriers is left as an exercise for the reader. This generally involves applying new constraints and a new target FPGA.

This example design showcases the functionality of the SZG-ENET1G. You may use this example design with two SZG-ENET1Gs and communicate between them, or with a single SZG-ENET1G by placing it into an internal PHY loopback test mode. The design utilizes a modified version of Xilinx’s Tri-Mode Ethernet MAC example design.

Xilinx’s Tri-Mode Ethernet MAC example design was created to target the KC705 or AC701 Xilinx development boards. The Xilinx example has been updated to replace the physical interfaces (DIP switches, pushbuttons, and LEDs) with FrontPanel virtual interface components. The Xilinx Example Design PHY configuration state machine has also been modified to configure the TI DP83867 PHY that is onboard the SZG-ENET1G peripheral. The original PHY (onboard the KC705 or AC701) configuration is similar, but there are subtle differences in these PHYs that make the original configuration incompatible. We have also added additional functionality to the original example design for more controllability and observation than what was provided by the original example design.

Sources

The sources for this example design are located at the following GitHub repository. You may acquire our generated bitfile in the most recent “Release” in this repository.

Requirements

Tutorials

Operate Single SZG-ENET1G

This tutorial will guide you through using a single SZG-ENET1G with this example reference design. You will accomplish placing your SZG-ENET1G into internal PHY loopback mode and then generating and receiving/checking packets.

  1. Download and install FrontPanel SDK version 5.2.5 or later. Version 5.2.5 adds support for the XEM8320.
  2. Turn off your XEM8320. 
  3. Plug a SZG-ENET1G into port A on your XEM8320.
  4. Connect your XEM8320 to your host PC with the provided USB cable. 
  5. Power on your XEM8320. 
  6. Open the FrontPanel application on your host PC.
  7. Configure your XEM8320 with the pre-built bitfile using the FrontPanel application.
  8. Open the EthernetExampleDesign.xfp XML file through the FrontPanel application to open the GUI. 
  9. Follow the instructions below in the “How To” section for “Place PHY in internal loopback mode and generate and check data on the same port.”

Operate using two SZG-ENET1Gs

This tutorial will guide you through using two SZG-ENET1Gs with this example reference design. You will accomplish generating and receiving/checking packets between two SZG-ENET1Gs.

  1. Download and install FrontPanel SDK version 5.2.5 or later. Version 5.2.5 adds support for the XEM8320.
  2. Turn off your XEM8320. 
  3. Plug a SZG-ENET1G into port A on your XEM8320.
  4. Plug a SZG-ENET1G into port C on your XEM8320.
  5. Connect both SZG-ENET1Gs together using an Ethernet cable.
  6. Connect your XEM8320 to your host PC with the provided USB cable. 
  7. Power on your XEM8320. 
  8. Open the FrontPanel application on your host PC.
  9. Configure your XEM8320 with the pre-built bitfile using the FrontPanel application. 
  10. Open the EthernetExampleDesign.xfp XML file through the FrontPanel application to open the GUI. 
  11. Follow the instructions below in the “How To” section for “Update MAC addresses and speed of communication between two SZG-ENET1Gs”
  12. Follow the instructions below in the “How To” section for “Generate data in one port and check that data on the other port”
  13. Follow the instructions below in the “How To” section for “Generate and check data in the same port and use the other port in HDL loopback mode”
  14. Experiment with some of the GUI settings listed in the “FrontPanel User Interface Reference” section.

Building the Gateware

Note:

Building the Ethernet Example Design is only supported in Vivado 2021.1.1 at this time.

A valid license for the Xilinx Tri-Mode Ethernet Media Access Controller (TEMAC) IP is required if you wish to build the project. You can request an evaluation license through the Xilinx website. The pre-built bitfile was built using this evaluation license.

  1. Acquire the sources for the Ethernet Example design on GitHub.
  2. Open Vivado GUI.
  3. Within the TCL console cd to the design-resources/ExampleProjects/EthernetExampleDesign/ directory containing project.tcl.
  4. Run source project.tcl
  5. Import FrontPanel HDL for your product into the project. These sources are located within the FrontPanel SDK installation.
  6. Generate Bitstream.

FrontPanel User Interface Reference

A picture of the GUI for this example design can be seen below:

KEY

Updating speed

  • Speed Advertised: Speed to advertise for auto-negotiation. 
  • Update Speed: Update the speed selected for auto-negotiation and restart auto-negotiation.

Observation

  • Link On LED: Link established indicator from the PHY.
  • Duplex On LED: Duplex enabled indicator from the PHY. 
  • RX Activity: Blink speed is relative to the speed of received packets.
  • Phy Neg Speed: Indicates the speed at which the PHY successfully negotiated the link. 00 = 10Mb/s, 01 = 100Mb/s, and 10 = 1000Mb/s

Controllability

  • Gen TX Data: Generate output data from this port at incrementing lengths.
  • Check RX Data: Check received generated data length.
  • PHY Loopback: Put the PHY in internal loopback mode. (Digital Loopback Mode)
  • Enable HDL Loopback: Send RX data back out onto the TX.
  • HDL Loopback Address Swap – When in HDL loopback mode this swaps the destination and source address before sending the data to the TX. This mode should be used when using an Ethernet protocol tester. 

Error

  • Error Occurred LED: Indicates that an error has occurred when checking the TX generated data that is received. This LED is sticky and must be reset.
  • Reset Error: Reset the sticky Error Occurred LED.
  • Inject Error: Injecting an error forces the generating data to not increment in length.

MAC address

  • Unique MAC address from EEPROM: This is the value of the unique MAC address for this SZG-ENET1G. This value is stored in the EEPROM device Pre-Programmed with a EUI-48™ MAC Address that has been assigned by the IEEE Registration Authority.
  • Set Port: This sets the destination and source address that was entered into the corresponding text box entries.
  • Set Addresses to Each Other: When two SZG-ENET1G pods are connected to port A and C this button sets the destination MAC address to that of the corresponding pod and the source address to that of the other pod. The values used for this come from the extracted MAC address from the EEPROMs on port A and C. 

How to use the Ethernet Reference Design

Update MAC addresses and speed of communication between two SZG-ENET1Gs

  1. Press “Set Addresses to Each Other” to use the EEPROM MAC addresses or use the default MAC addresses set upon reset. You may also set the MAC address manually through the entry box and press the “Set Port” button.
  2. Select the desired speed used for the autonegotiation mechanism. This speed must be the same for each port.
  3. Update speed in both port.
  4. Press “Reset Error” in both ports to reset the packet checker state machine associated with those ports.

Generate data in one port and check that data on the other port

  1. Check RX Data on the desired port.
  2. Gen TX data on the other port.
  3. Optionally Inject Error on port that is generating data.

Generate and check data in the same port and use the other port in HDL loopback mode

  1. Check RX Data on the desired port. 
  2. Enable HDL Loopback in the other port. 
  3. Gen Tx Data on the original desired port.
  4. Optionally Inject Error on port that is generating data.

Place PHY in internal loopback mode and generate and check data on the same port

  1. Set the MAC address manually through the entry box and press the “Set Port” button or use the default MAC addresses set upon reset.
  2. Select PHY loopback on desired port.
  3. Select the desired speed to configure into the PHY. 
  4. Update speed.
  5. Reset Error to restart the packet checker state machine.
  6. Check RX data.
  7. Gen TX data. 
  8. Optionally Inject Error.