Sample: Counters

This sample is a bit more complicated than the simple example and showcases a few more features of FrontPanel.

The Counters sample is a bit more complicated than the previous example.  It includes a few more FrontPanel components and also adds a few Trigger endpoints.  More importantly, though, it adds more hardware in the form of HDL so you can see how FrontPanel integrates with HDL in a slightly more complicated setup.

The FrontPanel virtual interface for this sample is shown below:

Hardware Description

The hardware for the Counters sample has two counters, the okHostInterface, a single Wire In endpoint, three Wire Out endpoints, and a Trigger In endpoint.  The hardware also routes to the LEDs on the XEM3001.

Counter #1

The first counter is an 8-bit up counter with enable, synchronous reset, and disable.  The enable signal is generated by a separate 24-bit counter to make the count progression slower.  The Verilog HDL for this counter and its clock divider counter is shown here:

always @(posedge clk1) begin div1 <= div1 - 1; if (div1 == 24'h000000) begin div1 <= 24'h400000; clk1div <= 1'b1; end else begin clk1div <= 1'b0; end if (clk1div == 1'b1) begin if (reset1 == 1'b1) count1 <= 8'h00; else if (disable1 == 1'b0) count1 <= count1 + 1; end end
Code language: PHP (php)

From the description, we gather that when RESET1 is asserted, the counter will hold the value 0x00.  When DISABLE1 is asserted, the counter holds its current value.  Otherwise, the counter will increment each time the clock divider counter expires.

Note that this counter operates on CLK1 which is mapped to LCLK1 on the PLL.

Counter #2

The second counter operates on CLK2 which is mapped to LCLK2 on the PLL.  Using the PLL Configuration Dialog, we will be able to observe the effects of changing the PLL frequencies on the two counters.

The Verilog HDL for this counter and its own divider is listed below.  This counter will count up when UP2 is asserted, count down when DOWN2 is asserted, and automatically count up when AUTOCOUNT2 is asserted.  Note that UP2 and DOWN2 must be asserted for exactly one CLK2 cycle for the counter to count only one.  This is why we have the Trigger endpoints.

always @(posedge clk2) begin div2 <= div2 - 1; if (div2 == 24'h000000) begin div2 <= 24'h100000; clk2div <= 1'b1; end else begin clk2div <= 1'b0; end if (reset2 == 1'b1) count2 <= 8'h00; else if (up2 == 1'b1) count2 <= count2 + 1; else if (down2 == 1'b1) count2 <= count2 - 1; else if ((autocount2 == 1'b1) && (clk2div == 1'b1)) count2 <= count2 + 1; end
Code language: PHP (php)

Endpoints

This sample uses several endpoints to provide controllable inputs to the hardware and observable outputs to FrontPanel.  To reduce the number of endpoints, we have chosen to share them among the counters.

Wire In (0x00)

The only Wire In endpoint is used to carry the RESET1, DISABLE1, and AUTOCOUNT2 signals.  These are wires because we want them to have a static state rather than one-shot signals.

SIGNALBIT(S)DESCRIPTION
RESET10When asserted, Counter #1 holds the value 0x00 and does not count.
DISABLE11When asserted, Counter #2 holds its value and does not count.
AUTOCOUNT22Configures counter #2 to autocount.
Unused15:3

Trigger In (0x40)

The only Trigger In endpoint is used for the Counter #2 inputs.  These are triggers because we want single events (one-shots) to occur, such as a count-up event.

Note that RESET2 behaves the same as RESET1 but we want to have RESET2 behave as a one-shot event so that the user cannot hold RESET2 asserted.  Therefore, we attach this one to a Trigger.

SIGNALBIT(S)DESCRIPTION
RESET20When asserted, Counter #2 resets to 0x00 and does not count.
UP21When asserted, Counter #2 counts up.
DOWN22When asserted. Counter #2 counts down.
Unused15:3

Wire Out (0x20, 0x21, and 0x22)

These wires provide observables for FrontPanel.  They are connected as follows:

ENDPOINTSIGNALDESCRIPTION
Wire Out 0x20COUNT1[7:0]Counter #1 value.
Wire Out 0x21COUNT2[7:0]Counter #2 value.
Wire Out 0x22BUTTON[3:0]The lower four bits of this wire bundle contain the status of the on-board pushbuttons.  If a button is pressed, the corresponding wire will be asserted.

FrontPanel Components

The user interface for the Counters sample includes two panels.  The first panel contains five buttons, four hex displays, eight LEDs, and a check box.  There are also two cosmetic components called okStaticBox which are used to group the components visually.  The second panel simply contains four LEDs used to display the state of the pushbuttons.

Panel 1: Counters Example

The active FrontPanel components are listed below with their corresponding endpoints:

COMPONENTLABELENDPOINTBIT
okPushbuttonReset0x000
okPushbuttonDisable0x001
okTriggerButton– Reset –0x400
okTriggerButton– Up –0x401
okTriggerButton– Down –0x402
okToggleCheckAutocount.0x002
okHexx[7:4]0x204
okHexx[3:0]0x200
okHexy[7:4]0x214
okHexy[3:0]0x210
okLED70x207
okLED6…10x206…1
okLED00x200

Note that the okLED and two of the okHex components share endpoint 0x20.  FrontPanel allows this and will update both components when Wire Out endpoints change.  It is also possible to map two components to input endpoints.

Panel 2: Pushbuttons

The second panel is not automatically opened when the Conters XFP file is loaded.  You can open it by pressing the number `2’ on your keyboard or navigating to

View → Pushbuttons

at the top of the FrontPanel window.  This displays a small window with the following components:

COMPONENTLABELENDPOINTBIT/MASK
okLED30x223
okLED20x222
okLED10x221
okLED00x220