Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM8320 may be found at the link to the right. 

Three software controlled dc-dc regulators power the three SYZYGY SmartVIO groups as assigned above. The behavior of these power supplies is determined by the XEM8320_SMARTVIO_MODE parameter in Device Settings and associated settings. The modes function as described below.

Note that, for modes that require a SmartVIO solution, if any peripheral provides non-compliant DNA, a SmartVIO solution cannot be reached for all groups.

• SmartVIO only – SmartVIO is tested collectively so all present SmartVIO peripherals must result in a collective validation for any of the outputs to be enabled.
• SmartVIO hybrid mode – Each group is individually tested for SYZYGY peripherals. Within each group, if a SYZYGY peripheral is present (via detection of compliant DNA data) on any of the ports within that group, the SmartVIO solution is used to determine the voltage setting. If no SYZYGY peripherals are detected within the group, then the corresponding Device Setting (e.g. XEM8320_VIO1_VOLTAGE) is used.
• Device Settings only – SmartVIO settings from the peripherals are ignored, only the device settings are used. Also note that, in this mode, SYZYGY peripheral discovery is not performed so the corresponding device settings that identify each peripheral are not populated.

The SmartVIO solution for each group is determined by the voltage range(s) supported by the corresponding FPGA I/O banks and the voltage range(s) supported by the peripherals, as reported in their respective SYZYGY DNA. The process is as follows:

1. The SmartVIO controller (XEM8320) queries all detected peripherals for their SYZYGY DNA.
2. The controller attempts to determine the lowest voltage that will satisfy all attached peripherals and FPGA ranges.
3. If a solution is not found, the group voltage remains disabled to protect any incompatible devices on the group.
4. If a solution is found, the group voltage is set to the voltage and enabled.

Peripherals that use LVDS may have a fixed or limited voltage range depending on the carrier. LVDS usage is stored as a flag in the peripherals SYZYGY DNA. Commonly this will limit the SmartVIO solution to 1.8V or 2.5V depending on the I/O bank type connected to the SYZYGY port (as with the XEM8320), but other voltages may be set depending on the specific FPGA requirements.

The SYZYGY +5V and +3.3V supplies are enabled during the firmware boot process. The switching regulator used for these supplies operates in a “light load mode” for efficiency when the load is relatively small. This light load operation can result in higher supply ripple, a common behavior among such supplies. This is normal, but may be higher than some applications desire. SYZYGY peripherals that are sensitive to high ripple should use additional power regulation on these supply rails.

The +5V and +3.3V regulators (Texas Instruments TPS54429E) include a light-load mode which increases regulator efficiency at the expense of output voltage ripple. In normal mode, the switching frequency is 700 kHz. In light-load mode, the effective switching frequency is reduced substantially (<10 kHz in some cases). The transition point between normal operation and light-load operation is dependent on the input supply voltage to the XEM8320, but typically occurs between 0.5 and 1.0 A output current. Output voltage ripple in light-load mode can be in the range of 50-100 mVpp.

SYZYGY ports A through C are connected to HP banks 66 and 67. These banks have their VRP pin connected to ground through a 240 ohm resistor. This is a requirement to use various high performance IOSTANDARDs.

Using these high performance IOSTANDARDs that utilize the VRP pins typically require strict pin placement to data and clock designated pins within the same IO byte group of a bank. Using the Pins Spreadsheet paired with the AU25P FFVB676 Package Device Pinout file, you’ll be able to make a correlation between the SYZYGY connector pin and the associated AMD full pin name, i.e., IO_L7N_T1L_N1_QBC_AD13N_66. Definitions of the various identifiers within the full name are at UG575.

Our provided schematics for the XEM8320-AU25P visualizes the AMD full pin name and the connection to the associated SYZYGY connector pin. Connections are listed in byte group ascending order which will help aid in verifying the strict pin requirements to data and clock designated pins.

The SZG-MIPI-8320 is an example peripheral that utilizes these VRP pins to use the MIPI_DPHY_DCI IOSTANDARD. The SZG-MIPI-8320’s documentation discusses this in more detail.

Single-ended fabric I/O are routed to the SYZYGY ports with 50Ω characteristic impedance. Differential fabric I/O and transceiver signals are routed to the SYZYGY ports as pairs with 100Ω differential impedance. Pin/package delay information may be obtained from the AMD design tools. The additional notes below also apply.

• Opal Kelly has matched fabric I/O routing to each SYZYGY port within 100 mil (2.54 mm). This matching includes the pin/package delays of the Artix UltraScale+.
• The length matching numbers in the compatibility tables below represent routed PCB lengths only and do not include the pin/package delays.
• Individual PCB routing lengths for all SYZYGY I/O (including transceivers) is available on the XEM8320 Pins Reference page. The lengths published there represent routed PCB lengths only and do not include the pin/package delays.

SYZYGY peripherals can be mechanically connected together using the carrier and peripheral mounting holes. Below are some suggested mounting hardware options. The Standard Hardware mounting kit is available from the accessories section of our store.

1. The I/O on this port do not support differential standards because of limitations on HD banks.
2. The C2P and P2C clock pins on these ports do not support differential standards because of limitations on HD banks.