SYZYGY Ports

Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM8320 may be found at the link to the right. 

 

Port Summary

PORTSYZYGY TYPESMARTVIO GROUP
AStandard1
BStandard1
CStandard1
DStandard2
ETransceiver3
FTransceiver3

Port Power

WARNING: “Device Settings Only” mode not recommended

The use of “Device Settings Only” mode is not recommended and may cause permanent damage to the XEM8320 or peripherals. This mode bypasses the SYZYGY SmartVIO power negotiation stage.

Three independent power regulators power the three SYZYGY SmartVIO groups as assigned above. The behavior of these power supplies is determined by the XEM8320_SMARTVIO_MODE parameter in Device Settings and associated settings. The modes function as described below.

Note that, for modes that require a SmartVIO solution, if any peripheral provides non-compliant DNA, a SmartVIO solution cannot be reached for all groups.

  • SmartVIO only – SmartVIO is tested collectively so all present SmartVIO peripherals must result in a collective validation for any of the outputs to be enabled.
  • SmartVIO hybrid mode – Each group is individually tested for SYZYGY peripherals. Within each group, if a SYZYGY peripheral is present (via detection of compliant DNA data) on any of the ports within that group, the SmartVIO solution is used to determine the voltage setting. If no SYZYGY peripherals are detected within the group, then the corresponding Device Setting (e.g. XEM8320_VIO1_VOLTAGE) is used.
  • Device Settings only – SmartVIO settings from the peripherals are ignored, only the device settings are used. Also note that, in this mode, SYZYGY peripheral discovery is not performed so the corresponding device settings that identify each peripheral are not populated.

+5V and +3.3V Supplies

The SYZYGY +5V and +3.3V supplies are enabled during the firmware boot process. The switching regulator used for these supplies operates in a “light load mode” for efficiency when the load is relatively small. This light load operation can result in higher supply ripple, a common behavior among such supplies. This is normal, but may be higher than some applications desire. SYZYGY peripherals that are sensitive to high ripple should use additional power regulation on these supply rails.

The +5V and +3.3V regulators (Texas Instruments TPS54429E) include a light-load mode which increases regulator efficiency at the expense of output voltage ripple. In normal mode, the switching frequency is 700 kHz. In light-load mode, the effective switching frequency is reduced substantially (<10 kHz in some cases). The transition point between normal operation and light-load operation is dependent on the input supply voltage to the XEM8320, but typically occurs between 0.5 and 1.0 A output current. Output voltage ripple in light-load mode can be in the range of 50-100 mVpp.

Length Matching

Single-ended fabric I/O is routed to the SYZYGY ports with 50Ω characteristic impedance. Differential fabric I/O is routed to the SYZYGY ports as 100Ω differential impedance. Pin/package delay information may be obtained from the Xilinx design tools. The additional notes below also apply.

  • Opal Kelly has matched fabric I/O routing to each SYZYGY port within 100 mil (2.54 mm). This matching includes the pin/package delays of the Artix UltraScale+.
  • The length matching numbers in the compatibility tables below represent routed PCB lengths only and do not include the pin/package delays.
  • Individual PCB routing lengths for all SYZYGY I/O (including transceivers) is available on the XEM8320 Pins Reference page. The lengths published there represent routed PCB lengths only and do not include the pin/package delays.

Port A SYZYGY Compatibility Table

PARAMETERPORT A
Port TypeStandard, Double-Width (with Port B)
Total 5V Supply Current4.5 A (Shared among all ports)
Total 3.3V Supply Current4.5 A (Shared among all ports)
VIO Supply Voltage Range1.0 V to 1.8 V
Total VIO Supply Current700 mA (shared among VIO Group 1 ports)
Port GroupGroup 1: A, B, C
I/O Count28 total (8 differential pairs)
Length3602 – 3943 mils (91.49 – 100.14 mm)
DP: ≤10 mils

Port B SYZYGY Compatibility Table

PARAMETERPORT B
Port TypeStandard, Double-Width (with Port A or Port C)
Total 5V Supply Current4.5 A (Shared among all ports)
Total 3.3V Supply Current4.5 A (Shared among all ports)
VIO Supply Voltage Range1.0 V to 1.8 V
Total VIO Supply Current700 mA (shared among VIO Group 1 ports)
Port GroupGroup 1: A, B, C
I/O Count28 total (8 differential pairs)
Length1994 – 2325 mils (50.64 – 59.07 mm)
DP: ≤10 mils

Port C SYZYGY Compatibility Table

PARAMETERPORT C
Port Type Standard, Double-Width (with Port B)
Total 5V Supply Current4.5 A (Shared among all ports)
Total 3.3V Supply Current4.5 A (Shared among all ports)
VIO Supply Voltage Range1.0 V to 1.8 V
Total VIO Supply Current700 mA (shared among VIO Group 1 ports)
Port GroupGroup 1: A, B, C
I/O Count28 total (8 differential pairs)
Length2963 – 3236 mils (75.26 – 82.19 mm)
DP: ≤10 mils

Port D SYZYGY Compatibility Table

PARAMETERPORT D
Port TypeStandard, Single-Width
Total 5V Supply Current4.5 A (Shared among all ports)
Total 3.3V Supply Current4.5 A (Shared among all ports)
VIO Supply Voltage Range1.2 V to 3.3 V
Total VIO Supply Current700 mA (VIO Group 2)
Port GroupGroup 2: D
I/O Count28 total (8 differential pairs)
Length3791 – 4176 mils (96.28 – 106.06 mm)
DP: ≤10 mils

Port E SYZYGY Compatibility Table

PARAMETERPORT E
Port TypeTransceiver (TXR4), Double-Width (with Port F)
Total 5V Supply Current4.5 A (Shared among all ports)
Total 3.3V Supply Current4.5 A (Shared among all ports)
VIO Supply Voltage Range1.2 V to 3.3 V
Total VIO Supply Current700 mA (shared among VIO Group 3 ports)
Port GroupGroup 3: E, F
I/O Count10 total
LengthStandard: 2731 – 2853 mils (69.36 – 72.47 mm)
XCVR: 1445 – 2282 mils (36.70 – 57.96 mm)
XCVR DP: ≤10 mils

Port F SYZYGY Compatibility Table

PARAMETERPORT F
Port TypeTransceiver (TXR4), Double-Width (with Port E)
Total 5V Supply Current4.5 A (Shared among all ports)
Total 3.3V Supply Current4.5 A (Shared among all ports)
VIO Supply Voltage Range1.2 V to 3.3 V
Total VIO Supply Current700 mA (shared among VIO Group 3 ports)
Port GroupGroup 3: E, F
I/O Count6 total
LengthStandard: 3130 – 3310 mils (79.49 – 84.08 mm)
XCVR: 2091 – 2928 mils (53.11 – 74.38 mm)
XCVR DP: ≤10 mils