Flash Memory

System Flash

The Flash memory attached to the USB microcontroller stores device firmware and settings as well as user data that is accessible via the FrontPanel API.  The API includes three methods for accessing this memory: FlashEraseSectorFlashWrite, and FlashRead.  Please refer to the FrontPanel User’s Manual and the FrontPanel API Reference for information about applying these methods.


The system flash (Cypress S25FS128SAGBHI200 or similar) is a 16 MiB Flash memory arranged into 256 64-kiB sectors.  Each sector contains 256 256-byte pages.  Sectors 0…15 are reserved for device firmware and settings and are not accessible to user software.  The remaining 15 MiB may be erased, written, and read using the FrontPanel API at any time even without a valid FPGA configuration.  Full 64 kiB sectors must be erased at a time.  However, contents may be read or written on any page address boundary.

FPGA Flash

The SPI Flash attached to the FPGA is an ISSI IS25WP256D-JLLE or equivalent.  It provides non-volatile storage for use by the FPGA.

The flash memory is connected to the FPGA configuration bank (Bank 0). The STARTUPE3 AMD primitive must be used to interface with the flash memory from a user design. See AMD UG570 UltraScale Architecture Configuration and the flashloader sample included with FrontPanel for more information.

The pins on the flash memory device are connected to the FPGA configuration bank according to the table below:

WPn/IO2D02_0AC114.75k Pull-Up
HOLDn/IO3D03_0AE114.75k Pull-Up
CEnRDWR_FCS_B_0AA122.49k Pull-Up

The M0_0, M1_0 and M2_0 configuration mode pins are controlled automatically by FrontPanel firmware for multiple configuration options. When the configuration is loaded from SPI FPGA flash, the configuration pins are setup as follows:

Configuration PINConfiguration PIN STate for SPI FLASH

Note: The Flash memory (as well as Bank 0 VCCO) is powered with 1.8V. Based on the device datasheet, this limits the maximum throughput to 104 MHz for fast read mode. Please see the Flash device data sheet for more details.

XDC Constraints for FPGA Flash Configuration

If you plan to utilize the FPGA Flash for configuring the FPGA at power-on, the Vivado software needs certain details about the FPGA flash to generate a suitable bitfile for this specific configuration mode. This bitfile is subsequently loaded into the FPGA flash. To accomplish this, implement the following XDC constraints within your project.

It is important to understand that if you generate bitfiles with the following constraints, they cannot be loaded through the FPGA Configuration Download feature in the FrontPanel application. Trying to do so will result in an error message stating FPGA configuration failed: Done did not go high.

set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 102.0 [current_design]Code language: CSS (css)

Loading a Power-On FPGA Configuration

The FPGA Flash may be used to store a bitfile to configure the FPGA at power-on. The Flash can be written using FrontPanel or through Vivado with a JTAG cable.

FrontPanel can be used to erase and program the power-on bitfile and the Flashloader sample is provided to perform these steps from a simple command-line utility.  Source code to the Flashloader sample is included with the FrontPanel SDK.

Using FrontPanel’s flash programming utility, apply the following settings:

  • Target: FPGA Flash
  • Data Type: Configuration
  • Start Sector: 0

Using the Flashloader sample, called with a single argument (the filename for a valid bitfile), the Flashloader sample will erase the first sectors in the FPGA Flash, then write the bitfile.

An FPGA configuration loaded in the FPGA Flash will always load at power on until the flash memory containing the configuration is cleared.