Gigabit Transceivers

In addition to the transceivers available through SYZYGY Ports E and F on banks 224 and 225 respectively, one transceiver quad is used to support SMA connections and two SFP+ modules (optional).

SFP+ Modules

Hot Plugging is Not Supported

While the SFP standard does support hot plugging of SFP+ modules, this is NOT SUPPORTED by the Artix UltraScale+ FPGA or the XEM8320.

Only insert or remove modules when power to the platform is turned off.

SFP1 and SFP2 transceiver signals are routed directly to Bank 226 transceivers. 0 Ohm series resistors are placed on the pairs.

SFP REFDESFPGA PINBANK REF
J13 (TD+)N5MGTYTXP0_226
J13 (TD-)N4MGTYTXN0_226
J13 (RD+)M2MGTYRXP0_226
J13 (RD-)M1MGTYRXN0_226
J14 (TD+)L5MGTYTXP1_226
J14 (TD-)L4MGTYTXN1_226
J14 (RD+)K2MGTYRXP1_226
J14 (RD-)K1MGTYRXN1_226

SFP1 and SFP2 control pins are routed through level translators to FPGA Bank 87, an HD bank. This allows the 3.3V I/O on the SFP modules to be compatible with whichever voltage is selected for bank 87 by the SYZYGY peripheral at SYZYGY Port D.

After level translation, these signals are routed to FPGA pins as shown in the table below.

SFP SignalSFP1 FPGA PinSFP2 FPGA PinUndriven Level
RATE_SELECT0D13B14HIGH
RATE_SELECT1E12A12HIGH
MOD_DEF0D14A14HIGH
MOD_DEF1C12G12HIGH
MOD_DEF2B12F12HIGH
LOSE13A13HIGH
TDISC13F13HIGH
TFAULTC14F14HIGH
TDNN4L4
TDPN5L5
RDNM1K1
RDPM2K2

SMA Connections

Six SMA connectors on the XEM8320 provide direct access to one transmit lane, one receive lane, and one reference clock on FPGA Bank 226.

0.1μF AC-coupling capacitors are installed between the SMA connectors and the FPGA for the MGTREFCLK1 P/N signals.

0.1μF AC-coupling capacitors are installed on the receive pairs. 0 Ohm series resistors are placed on the transmit pairs.

SMA REFDESFPGA PinBank Ref
J15 (RX+)H2MGTHRXP2_226
J16 (RX-)H1MGTHRXN2_226
J17 (TX+)J5MGTHTXP2_226
J18 (TX-)J4MGTHTXN2_226
J19 (REFCLK+)M7MGTREFCLK1P_226
J20 (REFCLK-)M6MGTREFCLK1N_226

Reference Clock

Along with the SMA reference clock connected to MGTREFCLK1, a 125 MHz fixed clock oscillator is connected to MGTREFCLK0 on Bank 226.

FPGA PinBank Ref
P7MGTREFCLK0P_226
P6MGTREFCLK0N_226

Impedance and Length Matching

All transceiver differential signals on the XEM8320 are routed with 100Ω differential impedance and all pairs are length matched to within 5mils.