Gigabit Transceivers

In addition to the transceivers available through SYZYGY Ports E and F on banks 224 and 225 respectively, one transceiver quad is used to support SMA connections and two SFP+ modules (optional).

SFP+ Modules

Hot Plugging is Not Supported

While the SFP standard does support hot plugging of SFP+ modules, this is NOT SUPPORTED by the Artix UltraScale+ FPGA or the XEM8320.

Only insert or remove modules when power to the platform is turned off.

SFP1 and SFP2 transceiver signals are routed directly to Bank 226 transceivers.

SFP1 and SFP2 control pins are routed through level translators to FPGA Bank 87, an HD bank. This allows the 3.3V I/O on the SFP modules to be compatible with whichever voltage is selected for bank 87 by the SYZYGY peripheral at SYZYGY Port D.

After level translation, these signals are routed to FPGA pins as shown in the table below.

SFP SignalSFP1 FPGA PinSFP2 FPGA Pin
RATE_SELECT0D13B14
RATE_SELECT1E12A12
MOD_DEF0D14A14
MOD_DEF1C12G12
MOD_DEF2B12F12
LOSE13A13
TDISC13F13
TFAULTC14F14
TDNN4L4
TDPN5L5
RDNM1K1
RDPM2K2

SMA Connections

Six SMA connectors on the XEM8320 provide direct access to one transmit lane, one receive lane, and one reference clock on FPGA Bank 226.

0.1μF AC-coupling capacitors are installed between the SMA connectors and the FPGA for the MGTREFCLK1 P/N signals.

0.1μF AC-coupling capacitors are installed on only the receive pairs.

SMA REFDESFPGA Pin
J15 (RX+)H2
J16 (RX-)H1
J17 (TX+)J5
J18 (TX-)J4
J19 (REFCLK+)M7
J20 (REFCLK-)M6

Reference Clock

Along with the SMA reference clock connected to MGTREFCLK1, a 125 MHz fixed clock oscillator is connected to MGTREFCLK0 on Bank 226.

Bank RefFPGA Pin
MGTREFCLK0P_226P7
MGTREFCLK0N_226P6

Impedance and Length Matching

All transceiver differential signals on the XEM8320 are routed with 100Ω differential impedance.