JTAG and SYSMON

JTAG

The JTAG connections on the FPGA are wired directly to a dedicated 2mm header (J3) compatible with the Xilinx JTAG cable. The JTAG interface presented is a 1.8v interface corresponding to the FPGA JTAG I/O voltage.

JTAG Cables

The USB interface on FrontPanel-enabled devices provides FrontPanel-based FPGA configuration and communication only. This interface is not available for JTAG access and is not compatible with the vendor tools for JTAG communication (i.e. Xilinx Vivado Integrated Logic Analyzer).

A vendor-supported JTAG cable is required to interface with the JTAG connector and provide tool access to JTAG. The JTAG cables listed below are available with connectors compatible with the connector on the XEM8320.

FPGA COMPATIBILITYMANUFACTURERCABLE P/N
XilinxDigilentJTAG-HS2
XilinxDigilentJTAG-HS3
XilinxXilinxPlatform Cable USB II

SYSMON

FPGA system monitor signals are available on a dedicated, non-populated 8-pin header at J4. The ADC signals are filtered through a simple RC network.

VREFP may optionally provide a precision reference for optimal performance of the ADC. See Xilinx UG580 UltraScale Architecture System Monitor for additional details.

By default, R211 (previously C62) is populated with a 0-Ω resistor so that the internal reference is used. If an external reference is used, this resistor must be removed and replaced with a 0.1-μF decoupling capacitor.

J4 pinConnection
1XADC_VP_C (FPGA P14)
2VCCADC (1.8V supplied by the XEM8320)
3XADC_VN_C (FPGA R13)
4Not Connected
5Not Connected
6Not Connected
7VREFN (FPGA P13)
8VREFP (FPGA R14)