JTAG and SYSMON

JTAG USB (Rev Cxx and Later)

On XEM8320 rev Cxx and later (purchased on or after 2023 July 28 or so), a vertical-launch USB Type-C connector provides JTAG access to the FPGA. This interface is supported by the vendor tools for JTAG communication (i.e. Vivado Integrated Logic Analyzer).

The direct access JTAG header (see the Bxx header information below) is still available on revision Cxx boards, but the header connector is not placed by default. The connector (Molex 87831-1420 or compatible) would need to be placed to use the direct JTAG connections.

JTAG Header (Rev Bxx and Earlier)

The JTAG connections on the FPGA are wired directly to a dedicated 2mm header (J3) facilitate FPGA configuration and ChipScope usage using a JTAG cable. The JTAG interface presented is a 1.8V interface corresponding to the FPGA JTAG I/O voltage. The TMS, TCK and TDI signals are pulled to 1.8V via 4.75k resistors.

The JTAG header component is not placed on Rev Cxx and later, but one may be added to the header location.

CONNECTOR PINJTAG SIGNALCONNECTOR PINJTAG SIGNAL
1GND2+1.8V (Vref)
3GND4JTAG_TMS
5GND6JTAG_TCK
7GND8JTAG_TDO
9GND10JTAG_TDI
11GND12NC
13GND14NC

JTAG Cables

The USB interface on FrontPanel-enabled devices provides FrontPanel-based FPGA configuration and communication only. This interface is not available for JTAG access and is not compatible with the vendor tools for JTAG communication (i.e. Vivado Integrated Logic Analyzer).

A vendor-supported JTAG cable is required to interface with the JTAG connector and provide tool access to JTAG. The JTAG cables listed below are available with connectors compatible with the connector on the XEM8320.

FPGA COMPATIBILITYMANUFACTURERCABLE P/N
AMDDigilentJTAG-HS2
AMDDigilentJTAG-HS3
AMDAMDPlatform Cable USB II

SYSMON

FPGA system monitor signals are available on a dedicated, non-populated 8-pin header at J4. The ADC signals are filtered through a simple RC network.

VREFP may optionally provide a precision reference for optimal performance of the ADC. See AMD UG580 UltraScale Architecture System Monitor for additional details.

By default, R211 (previously C62) is populated with a 0-Ω resistor so that the internal reference is used. If an external reference is used, this resistor must be removed and replaced with a 0.1-μF decoupling capacitor.

J4 pinConnection
1XADC_VP_C (FPGA P14)
2VCCADC (1.8V supplied by the XEM8320)
3XADC_VN_C (FPGA R13)
4Not Connected
5Not Connected
6Not Connected
7VREFN (FPGA P13)
8VREFP (FPGA R14)