In addition to the power LED, there are six LEDs, each of which is controlled by FPGA pins as shown in the table below.
The LED anodes are connected to a pull-up resistor to +3.3 V and the cathodes wired through NMOS transistors to the FPGA I/O on Bank 66 and Bank 67. Both banks are powered by VIO1 which is shared with SYZYGY ports A, B, and C. To turn ON an LED, the FPGA pin should be at logic ‘1’. To turn OFF an LED, the FPGA pin should be at logic ‘0’.
The I/O voltage for Banks 66 and 67 is set by VIO1 which is controlled by SYZYGY SmartVIO or (optionally) Device Settings. The FET circuit described above effectively provides voltage translation and allows the LEDs to work with any supported voltage.