DDR4 Memory

The 1-GiByte DDR4 SDRAM provides a 16-bit wide data interface and is connected exclusively to the 1.2-V I/O on HP bank 64 of the FPGA. The maximum data rate of the SDRAM is 2666 Mb/s, although the speed grade of the Artix UltraScale+ will limit the maximum supported data rate to what is stated in Table 27 of DS931. The -2 speed grade on the XEM8320-AU25P supports a maximum data rate of 2400 Mb/s. This gives a supported peak memory bandwidth of 38.4 Gb/s.

The following resources are available to help provide guidance for designs that involve this memory:

MIG Settings

Artix UltraScale+ devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by AMD. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on the DDR4 SDRAM (MIG) v2.2 IP and Vivado 2022.1. This configuration sets up the correct MMCM M/D values to use an exact 100MHz reference input clock to achieve exactly 2400 Mb/s performance. This is a contradiction to the GUI reported 100.04Mhz for the selection of “9996” for “Reference Input Clock Speed (ps).” Please see AMD Article 66554 for more information regarding a similar situation.

Timing will constrain the DDR4 reference clock to 100.04Mhz in this case, which is a more pessimistic constraint versus 100Mhz. This results in the user losing 1.33 ps of usable slack for timing closure on the `c0_ddr4_ui_clk` MIG user interface clock. This is negligible and won’t produce metastable/non-functional designs due to this being a more pessimistic constraint. For this reason, we use the MIG’s propagated constraint of 100.04Mhz on the DDR4 ref clk within all our provided samples.

If an additional 1.33 ps of slack is required to meet timing, you may constrain the DDR4 ref clk to 100 Mhz in a top level constraints file and ignore the critical warnings that come as a result of overwriting this.

PARAMETERXEM8320-AU25P
Controller TypeDDR4 SDRAM
Controller/PHY ModeController and physical layer
Memory Device Interface Speed (ps)833
PHY to controller clock frequency ratio4:1
Reference Input Clock Speed (ps)9996
ConfigurationComponents
Memory PartMT40A512M16LY-075
SlotSingle
IO Memory Voltage1.2V
Data Width16
ECC Disabled
Data Mask and DBIDM NO DBI
Memory Address MapROW COLUMN BANK
OrderingNormal
Cas Latency17
Cas Write Latency12
Force Read and Write commands to use AutoPrechargeDisabled
Clamshell TopologyDisabled
Enable AutoPrecharge InputDisabled
Enable User Refresh and ZQCS InputDisabled
Advanced optionsDefault

DDR4 / FPGA Pin Connections

The FPGA to DDR4 pin mappings are shown below. These are also available in the Pins Reference when exporting a constraints file as well as the sample designs that utilize the memory.

DDR4 PINFPGA PIN
RESETAE26
CK_tY20
CK_cY21
CKEAA20
CSAF22
DQSL_tAC26
DQSL_cAD26
DQSU_tAA22
DQSU_cAB22
DM0AE25
DM1AE22
ACTY18
ODTAB20
DDR4 PINFPGA PIN
A0AD18
A1AE17
A2AB17
A3AE18
A4AD19
A5AF17
A6Y17
A7AE16
A8AA17
A9AC17
A10 / APAC19
A11AC16
A12 / BCAF20
A13AD16
A14 / WEAA19
A15 / CASAF19
A16 / RASAA18
BA0AC18
BA1AF18
BG0AB19
DDR4 PINFPGA PIN
D0AF24
D1AB25
D2AB26
D3AC24
D4AF25
D5AB24
D6AD24
D7AD25
D8AB21
D9AE21
D10AE23
D11AD23
D12AC23
D13AD21
D14AC22
D15AC21