In addition to the USB host interface clock, three fixed-frequency clock oscillators provide reference clocks for various FPGA components and systems. Below we define names for these clocks, and discuss potential use cases.
|CLOCK||FREQUENCY||FPGA Pins (P / N)|
|Fabric||100 MHz||T24 / U24 (Bank 65)|
|DDR4||100 MHz||AD20 / AE20 (Bank 64)|
|MGT||125 MHz||P7 / P6 (Bank 226)|
General Purpose Clocks:
The Artix UltraScale Plus’s Clock Management Tiles (CMTs) are located adjacent to each of the 4 HP banks available on the XEM8320-AU25P. Each CMT contains one MMCM and two PLLs that can be used for various clocking features. The two general purpose clock oscillators are routed to clock capable pins of HP banks, allowing direct access to their bank’s CMT or access to the clock tree to reach other parts of the die with minimal skew. Both clocks are LVDS, terminated, biased, and AC-coupled following the circuit laid out in Figure 1‐83 of UG571.
- Fabric Clock – This clock is attached to HP bank 65. This is the same bank the FrontPanel okHost is connected to. The FrontPanel okHost makes use of the only MMCM for bank 65. To use an MMCM’s features with this reference clock, one must accept a non-ideal route outside of bank 65, using the low skew clock tree, to an MMCM within another bank. This is accomplished using a
set_property CLOCK_DEDICATED_ROUTE BACKBONEconstraint. Alternatively, use of the two available PLLs within bank 65’s CMT can be used. If no CMT functionality is required, this clock can be used to clock BELs throughout the FPGA die using the clock tree.
- DDR4 Clock – This clock and the DDR4 SDRAM are both attached to HP bank 64. This clock provides a direct connection to the MMCM used by Xilinx’s MIG IP within bank 64. 100MHz is used to achieve the clock frequencies necessary for DDR4-2400. When not using the DDR4 memory in a design, this clock can be used as a second general purpose
Transceiver Reference Clock:
- MGT Clock – A 125MHz reference clock connected to
MGTREFCLK0on transceiver bank 226. Bank 226 provides access to the SFP and SMA transceiver lanes.
Reference clocks connected to the transceiver banks only have direct connection to the QPLLs and CPLLs within the transceiver bank’s COMMON block. The QPLL and CPLL have limited ability to multiply and divide a reference clock, making a fixed frequency reference clock unable to satisfy all protocol line rates (DisplayPort, JESD, HDMI, 10G Ethernet, etc.). Our provided fixed clock oscillator is intended to quickly realize line rate multiples up to and including the max for the GTY transceivers (16.375Gbs).
If a frequency of 125MHz fails to satisfy the reference clock requirements for your SFP evaluation, you must use bank 226’s
MGTREFCLK1 can be accessed through a pair of SMA connectors on the XEM8320-AU25P.