There are 41 signals that connect each on-board USB microcontroller to the FPGA. These signals comprise the host interface on the FPGA. The primary USB microcontroller host interface is capable of performing configuration downloads. After configuration, the host interface signals on both USB microcontrollers are used to allow FrontPanel communication with the FPGA.

If the FrontPanel okHost module is instantiated in your design, you must map the interface pins to specific pin locations using Xilinx PACKAGE_PIN constraints. This may be done using the Xilinx constraints editor or specifying the constraints manually in a text file. Please see the sample projects included with your FrontPanel installation for examples. In particular, the Counters and PipeTest samples incorporate both USB microcontrollers in their designs.

The okHost module provides a 100.8 MHz clock to your design that is synchronous to the host interface. This clock must be used for all pipe interfaces unless clock synchronizers (e.g. asynchronous FIFOs) are used to cross a clock boundary to another system clock.

Pin AP14 of the FPGA is an active-high BOARD_READY signal from the host interface. This signal is asserted high when all board specific configuration is completed by the firmware, which includes setting up device sensors and configuring adjustable bank voltage rails. The signal will remain asserted from then on, and is not de-asserted during configuration. Configurations loaded in FPGA flash may complete configuration before the signal is asserted, depending on their size.

The USB host interface includes Opal Kelly’s proprietary microcontroller firmware and proprietary HDL modules. Opal Kelly does not provide schematics or documentation for the inner workings of this interface. Everything you need to know to deploy the host interface in your application is documented in the FrontPanel User’s Manual. As part of the FrontPanel SDK, several examples are included for each board. Pins should be used to generate a reference constraints file for your HDL design.

The XEM8350 provides two fully independent USB 3.0 host interface connections. The primary interface is capable of configuring the FPGA and handles the Device Settings and Device Sensors for the board. An FPGA design utilizing both interfaces is capable of transmitting and receiving data at full FrontPanel data rates (over 340 MB/s) through each interface.

The two host interfaces each operate on their own clock domain and are asynchronous to each other. Data passing between the two interfaces must be synchronized to the corresponding clock domain for each interface.

The I/O for each interface must be passed to the okHost module. The okHost module provides separate clock and okHE/okEH busses for each interface. The secondary interface is differentiated by the use of an ‘s‘ appended to nets associated with the secondary interface.

The FrontPanel API enumerates the primary interface with the product name (ie. XEM8350-KU060, etc). The secondary interface always enumerates as “XEM8350-SECONDARY”. The serial number for the secondary interface is identical to that of the primary interface with the 5th digit replaced by a 1. For example, a serial number of “1930000ABC” on the primary interface will have a serial number of “1930100ABC” on the secondary interface.

For users who need the secondary host interface, it’s essential to utilize the okDone signal. However, if you’re not using the secondary host interface, there’s no need for the okDone signal. The primary interface is responsible for configuring the device. Once configured, the primary interface communicates readiness to the secondary host interface through the okDone signal. Refer to our provided Counters or PipeTest samples for a demonstration of how to use the okDone signal.

The shells of the USB-C connectors are terminated to circuit ground using a 0.1-uF capacitor in parallel with a 220-ohm ferrite bead. Three uninstalled zero-ohm resistors on each connector allow optional direct (DC) connection of the shell to circuit ground if desired.