Device Settings
The XEM8320 supports the FrontPanel Device Settings in the table below, accessible from the FrontPanel Application as well as the Device Settings API.
Note: All VIO and SZG device settings require a power cycle to take effect.
All XEM8350 version manufactured after 2021-01-11 include low VIO support (XEM8350_LOW_VIO_SUPPORT reads as 1).
| NAME | TYPE | DESCRIPTION |
|---|---|---|
| XEM8350_VIO1_VOLTAGE | INT32 | VIO1 output voltage specified in 10’s of mV. For example, “180” would set VIO1 = 1.8V. This rail has a valid range of 0.95V to 1.8V (1.2V to 1.8V on boards where XEM8350_LOW_VIO_SUPPORT reads as 0). DEFAULT: 0 (output is disabled) |
| XEM8350_VIO2_VOLTAGE | INT32 | VIO2 output voltage specified in 10’s of mV. For example, “180” would set VIO2 = 1.8v. This rail has a valid range of 0.95V to 1.8V (1.2V to 1.8V on boards where XEM8350_LOW_VIO_SUPPORT reads as 0). DEFAULT: 0 (output is disabled) |
| XEM8350_VIO_MODE | INT32 | 0x00 – IPMI with Device Settings fallback – IPMI is used to set the VIO voltages. If an IPMI EEPROM is not found, Device Settings will determine the output voltages. 0x01 – IPMI only – IPMI is used to set the VIO voltages. 0x02 – Device Settings only – VIO voltages are set through the VIOx_VOLTAGE device settings. 0x03 – SmartVIO only (see below) – SmartVIO is tested collectively so all present SmartVIO peripherals must result in a collective validation for any of the outputs to be enabled. DEFAULT: 0 |
| XEM8350_LOW_VIO_SUPPORT FW 1.35+ | INT32 | A read-only setting. 1 – The VIO valid range is from 0.95V to 1.8V 0 – The VIO valid range is from 1.2V to 1.8V |
| XEM8350_SZG_TXR4_PORTS | INT32 | Bitfield used to indicate which SYZYGY ports (of the 16 possible ports) are TXR4 ports. Each bit represents a SYZYGY port, with bit 0 corresponding to the first SYZYGY address and bit 15 corresponding to the last SYZYGY address. A ‘1’ indicates that a particular port is a TXR4 port. For BRK8350 revision FXX and older this value should be set to 0x0C00For BRK8350 revision HXX and newer this value should be set to 0x00C0 |
| XEM8350_FAN_MODE | INT32 | 0=Binary mode 1=Temperature controlled mode DEFAULT: 0 |
| XEM8350_FAN_ENABLE | INT32 | In binary mode, 0=disable, 1=enable DEFAULT: 1 |
| XEM8350_FAN_TEMP_THRESHOLD FW 1.35 and before | INT32 | In temperature controlled mode, the number here represents the lower threshold (in degrees Celsius) for temperature-dependent operation. At THRESH, fan control PWM=0% At THRESH+16C, fan control PWM=50% At THRESH+32C, fan control PWM=100% DEFAULT: 16C |
| XEM8350_FAN_TEMP_THRESHOLD FW 1.49+ | INT32 | In temperature controlled mode, the number here represents the threshold (in degrees Celsius) for fan enable. At THRESH, fan is enabled At THRESH-10C, fan is disabled DEFAULT: 16C |
Fan Control Device Settings
You may optionally connect a fan to J4 (Molex 53398-0271). This connector drives the input voltage to the fan according to the Device Settings. For most applications, we recommend binary operating mode and enabling the fan at all times. You may optionally configure fan control based on the FPGA die temperature. See the Specifications page for more information on the FanSink.
Note: Make sure the input voltage is an appropriate value for the connected fan.
SYZYGY SmartVIO
The SmartVIO mode is intended for carriers that implement SYZYGY ports. In SYZYGY SmartVIO mode the VIO voltage is determined by first reading the SYZYGY DNA of all SYZYGY peripherals then solving for a SmartVIO solution. Each of the three XEM8370 VIO rails corresponds to a SYZYGY VIO group. The first 4 SYZYGY ports (ports 0 to 3) are assigned to VIO1, with the next 6 SYZYGY ports (ports 4 to 9) assigned to VIO2, and the next 6 SYZYGY ports (ports 10 to 15) assigned to VIO3. The SYZYGY port ID is determined by the ports geographical address resistor as specified in the SYZYGY DNA Specification. When XEM8350_VIO_MODE is set to 0x03, all ports are scanned for peripherals and entered into the SmartVIO solver to determine what VIO voltage will be set. The process is as follows:
- The SmartVIO controller (XEM8350) queries all detected peripherals for their SYZYGY DNA.
- For each SYZYGY VIO group, the controller attempts to determine the lowest voltage that will satisfy all attached peripherals and FPGA ranges.
- If a solution is not found, the group voltage remains disabled to protect any incompatible devices on the group.
- If a solution is found, the group voltage is set to the voltage and enabled.
| SYZYGY PORT | VIO GROUP | GEOGRAPHICAL ADDRESS (I2C ADDRESS) | R_GA ADDRESS RESSISTOR (KΩ) |
|---|---|---|---|
| SYZYGY 0 | VIO1 | 0x30 0b0110 000x | 210 |
| SYZYGY 1 | VIO1 | 0x31 0b0110 001x | 84.5 |
| SYZYGY 2 | VIO1 | 0x32 0b0110 010x | 49.9 |
| SYZYGY 3 | VIO1 | 0x33 0b0110 011x | 34.0 |
| SYZYGY 4 | VIO1 | 0x34 0b0110 100x | 24.9 |
| SYZYGY 5 | VIO1 | 0x35 0b0110 101x | 18.7 |
| SYZYGY 6 | VIO1 | 0x36 0b0110 110x | 14.3 |
| SYZYGY 7 | VIO1 | 0x37 0b0110 111x | 11.3 |
| SYZYGY 8 | VIO2 | 0x38 0b0111 000x | 8.87 |
| SYZYGY 9 | VIO2 | 0x39 0b0111 001x | 6.98 |
| SYZYGY 10 | VIO2 | 0x3A 0b0111 010x | 5.36 |
| SYZYGY 11 | VIO2 | 0x3B 0b0111 011x | 4.02 |
| SYZYGY 12 | VIO2 | 0x3C 0b0111 100x | 2.94 |
| SYZYGY 13 | VIO2 | 0x3D 0b0111 101x | 2.00 |
| SYZYGY 14 | VIO2 | 0x3E 0b0111 110x | 1.18 |
| SYZYGY 15 | VIO2 | 0x3F 0b0111 111x | 0.487 |
IPMI Controlled VIO
The XEM8350 adjustable voltage rails can be configured automatically by the carrier board. This requires a compatible EEPROM to be included and programed on the carrier board. For more information see the Adjustable I/O Voltages section of the Expansion Connectors page.