DDR4 Memory

The Micron DDR4 SDRAM is connected exclusively to the 1.2-V I/O on Banks 66, 67, and 68 of the FPGA. The tables below list these connections.

The following resources are available to help provide guidance for designs that involve this memory:

  • The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
  • The XEM8350 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

XEM8350-KU115

The XEM8350-KU115 built with PCB revision Dxx uses PCB routing designed to match the KU060 package routing lengths. Some derating may be required to meet timing at all timing corners.

Please contact [email protected] for additional information and guidance.

Connection Tables

DDR4 PINFPGA PIN
RESETK23
CKpL20
CKnK20
CKEK21
CSH21
DQS0_tC12
DQS0_cB12
DQS1_tC17
DQS1_cB17
DQS2_tF13
DQS2_cF12
DQS3_tF17
DQS3_cE17
DQS4_tK13
DQS4_cK12
DQS5_tK16
DQS5_cJ16
DQS6_tN12
DQS6_cM12
DQS7_tT18
DQS7_cT17
DQS8_tN21
DQS8_cN22
DM0A13
DM1D19
DM2F15
DM3H19
DM4J13
DM5L17
DM6P13
DM7P19
DM8T23
DDR4 PINFPGA PIN
A0D23
A1A23
A2F24
A3C23
A4G24
A5F22
A6D21
A7B24
A8C21
A9E22
A10H24
A11C22
A12B22
A13A24
A14 / WEbL22
A15 / CASG22
A16 / RASH22
BA0K22
BA1A22
BG0G21
DDR4 PINFPGA PIN
D0B16
D1C14
D2B14
D3C13
D4B15
D5D13
D6A15
D7A14
D8A19
D9C18
D10B20
D11A17
D12A20
D13D18
D14A18
D15B19
DDR4 PINFPGA PIN
D16E13
D17G14
D18E12
D19D16
D20D14
D21E16
D22D15
D23F14
D24F20
D25F19
D26E18
D27F18
D28E20
D29G20
D30H17
D31H18
DDR4 PINFPGA PIN
D32J14
D33J15
D34G16
D35L12
D36H14
D37K15
D38G15
D39L13
D40J18
D41M16
D42J19
D43K18
D44J20
D45L18
D46M17
D47L19
DDR4 PINFPGA PIN
D48L15
D49R12
D50N14
D51R13
D52M15
D53P15
D54M14
D55P14
D56N18
D57N19
D58N17
D59R16
D60N16
D61R18
D62P16
D63R17
DDR4 PINFPGA PIN
D64P20
D65T22
D66R20
D67R22
D68P21
D69P23
D70N23
D71R21

MIG Settings

Kintex UltraScale devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on MIG 2.2 and Vivado 2021.1.

PARAMETERXEM8350-KU060
Controller TypeDDR4 SDRAM
Controller/PHY ModeController and physical layer
Memory Device Interface Speed (ps)938
PHY to controller clock frequency ratio4:1
Reference Input Clock Speed (ps)6566
ConfigurationComponents
Memory PartMT40A512M16LY-075
SlotSingle
IO Memory Voltage1.2V
Data Width72
ECCOptional (Enabled for RAMTester sample)
Data Mask and DBINO DM NO DBI
Memory Address MapROW COLUMN BANK
OrderingNormal
Cas Latency15
Cas Write Latency11
Force Read and Write commands to use AutoPrechargeDisabled
Clamshell TopologyDisabled
Enable AutoPrecharge InputDisabled
Enable User Refresh and ZQCS InputDisabled
Advanced optionsDefault