Product Lifecycle

Firmware Version History

Please visit the FrontPanel Firmware page for firmware version information. Firmware updates are provided through the FrontPanel Application. Please see the Firmware Updates page for instructions on updating your device firmware. You will need to have a valid Pins registration and be approved for firmware downloads.

HDL Version History

XEM8350s purchased in 2022 and later will require the FrontPanel HDL from FrontPanel SDK version 5.2.5 or later. An XEM8350 in this category will not work with FrontPanel HDL from earlier FrontPanel SDK versions.

XEM8350 PCB Version History

XEM8350-KU060BXXFirst production PCB.
XEM8350-KU060DXXImproved transceiver routing signal integrity.
Improved assembly yield.

The PCB revision is identified in the board silkscreen.

XEM8350-KU060 Rev DXX

Revision DXX is shipped for orders on or after 2020-11-20.

Several PCB routing optimizations were made to improve assembly qualification yield and transceiver signal integrity.  These changes are form/fit/function compatible with existing product at revision BXX.

BRK8350 PCB Version History

BRK8350EXXFirst production PCB.
BRK8350FXXReverse ordering of QSFP RX lane.
BRK8350GXXUpdated QSFP and M.2 control signals.
Added synchronous PCIE clock for M.2 slot.
Updated SYZYGY port IO connections.
Updated QSFP lane ordering.
Improved JTAG compatibility with some adapters.

BRK8350 Rev FXX

Revision FXX is shipped for all order shipped on or after 2021-02-11.

The GTH RX lanes on connectors QSFP1 and QSFP2 where connected in the reverse order of the GTH TX lanes between expansion connector MC3 and the QSFP1 and QSFP2 connectors. RX Lane 1 of each connector was connected to RX Lane 4 of the corresponding GTH quad. TX Lane 1 of each connector was connected to TX Lane 1 of the corresponding GTH quad.  This can result in problems with some protocols that require that each lane be connected in order for both RX and TX.  This can also result in issues where channels within the quad are used individually, as the RX and TX lanes will be connected to separate channels.

The issue has been resolved by ensuring that the QSFP RX lanes are connected in the same order as the QSFP TX lanes (i.e. QSFP1_RXP/N connected to RX channel 1 of the corresponding quad, just as QSFP1_TX1P/N are connected to TX channel 1 of the corresponding quad).

BRK8350 Rev GXX

Connections to the SYZYGY ports and QSFP transceivers have been updated for higher compatibility. See the Pins Page Rev GXX columns for full connection details.

The QSFP and M.2 control signal connections have been updated to comply with their associated specification standards.

A PCIE Gen 3 compliant synchronous clock generator was added to replace the discrete oscillators. This clock is provided to the M.2 slot and a transceiver ref clock. For more details see the BRK8350 page.

Digilent JTAG adapters did not function reliably on past BRK8350 revisions. This has been resolved in Rev GXX.

Product Change Notifications

Product Change Notifications (PCN) are issued if a change to the product results in a change of mechanical or electrical behavior or reliability.

  • PCN-10079 – Remedy for incorrect set resistor installed on early production units for VCCINT power converter.
    Issue Date: 2021-01-01