PCB Version History
|First production PCB.
|Reverse ordering of QSFP RX lane.
|Updated QSFP and M.2 control signals.
Connected M.2 to PCIE hard block adjacent Quad.
Added synchronous PCIE clock for M.2 slot.
Updated SYZYGY port IO connections.
Updated QSFP lane ordering.
Improved JTAG compatibility with some adapters.
BRK8350 Rev FXX
Revision FXX is shipped for all order shipped on or after 2021-02-11.
The GTH RX lanes on connectors QSFP1 and QSFP2 where connected in the reverse order of the GTH TX lanes between expansion connector MC3 and the QSFP1 and QSFP2 connectors. RX Lane 1 of each connector was connected to RX Lane 4 of the corresponding GTH quad. TX Lane 1 of each connector was connected to TX Lane 1 of the corresponding GTH quad. This can result in problems with some protocols that require that each lane be connected in order for both RX and TX. This can also result in issues where channels within the quad are used individually, as the RX and TX lanes will be connected to separate channels.
The issue has been resolved by ensuring that the QSFP RX lanes are connected in the same order as the QSFP TX lanes (i.e. QSFP1_RXP/N connected to RX channel 1 of the corresponding quad, just as QSFP1_TX1P/N are connected to TX channel 1 of the corresponding quad).
BRK8350 Rev HXX
Connections to the SYZYGY ports and QSFP transceivers have been updated for higher compatibility. See the Pins Page Rev HXX columns for full connection details.
The QSFP and M.2 control signal connections have been updated to comply with their associated specification standards.
The M.2 transceiver connections where moved to a quad that is adjacent to a PCIE hard block so that PCIE can be used with the slot.
A PCIE Gen 3 compliant synchronous clock generator was added to replace the discrete oscillators. This clock is provided to the M.2 slot and a transceiver ref clock. For more details see the BRK8350 page.
Digilent JTAG adapters did not function reliably on past BRK8350 revisions. This has been resolved in Rev HXX.