Expansion Connectors

Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM8350 may be found at the link to the right.

 

Fan Power Supply

A small 2-pin connector (Molex 53398-0271) at J4 provides power to an optional fansink for FPGA cooling. This fan is controlled by a digital fan controller as part of the Device Sensors and Device Settings capabilities. Please see the Device Settings section for details on controlling the fan.

The fansink is powered directly by the +VDCIN input voltage to the XEM8350. The allowable range for +VDCIN is 5-16 VDC. When utilizing the Opal Kelly FANSINK-40X40, it is recommended to use an input voltage within the specified operating range of the fansink: 6-13.8 VDC.

PINSIGNAL
1GND
2+VDCIN

Expansion Connectors

The XEM8350 uses three high-density Samtec connectors to provide access to 420 signals on the module. These are precision connectors and may have a high insertion / removal force. To prevent damage to the module, PCB, connectors, and other components on the board, it is important to mate and un-mate the module from the base board carefully.

The BRK8350 includes a set of Samtec JSO jack screw standoffs to aid in assembly and disassembly of the XEM8350 to the BRK8350. We recommend similar mechanical design for any board that mates to the XEM8350.

Please visit our Jack Screw Instructions for more information.

Two high-density, 180-pin expansion connectors are available on the bottom-side of the XEM8350 PCB. A third high data rate optimized 120-pin expansion connector is provided on the bottom-side of the XEM8350 PCB. These expansion connectors provide user access to several power rails on the XEM8350, the JTAG interface on the FPGA, and 332 dedicated I/O pins on the FPGA, including several global clock inputs. High-speed gigabit transceiver signals are also available through these expansion connectors.

The MC1 and MC2 connectors on the XEM8350 are Samtec part number: QSH-090-01-L-D-A.  The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-090-01-F-D-A part is used on the BRK8350 breakout board.

SAMTEC PART NUMBERMATED HEIGHT
QTH-090-01-F-D-A5.00mm (0.197″)
QTH-090-02-F-D-A8.00mm (0.315″)
QTH-090-03-F-D-A11.00mm (0.433″)
QTH-090-04-F-D-A16.00mm (0.630″)
QTH-090-05-F-D-A19.00mm (0.748″)
QTH-090-07-F-D-A25.00mm (0.984″)

The MC3 connector on the XEM8350 is Samtec part number: QSH-060-01-L-D-DP-A.  The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-060-01-L-D-DP-A part is used on the BRK8350 breakout board.

SAMTEC PART NUMBERMATED HEIGHT
QTH-060-01-L-D-DP-A5.00mm (0.197″)
QTH-060-02-L-D-DP-A8.00mm (0.315″)
QTH-060-03-L-D-DP-A11.00mm (0.433″)
QTH-060-04-L-D-DP-A16.00mm (0.630″)
QTH-060-05-L-D-DP-A19.00mm (0.748″)
QTH-060-07-L-D-DP-A25.00mm (0.984″)

Jack Screw Standoffs

The XEM8350 uses Samtec Jack Screw Standoffs to ensure even mounting and un-mounting pressure when connecting to a base board. The table below lists the appropriate Samtec Jack Screw Standoffs along with the total mated height. The JSO-0515-01 part is used on the BRK8350 breakout board. Samtec Jack Screw Standoffs are sold as a set consisting of the base, jack screw, washer, and mounting screw. Four Jack Screw Standoffs are required to mount the XEM8350 to a base board.

SAMTEC PART NUMBERMATED HEIGHTBASE BOARD CONNECTION STYLE
JSO-0515-015.00mm (0.197″)Press fit
JSO-0815-018.00mm (0.315″)Press fit
JSO-0815-03-L8.00mm (0.315″)Threaded
JSO-1115-03-L11.00mm (0.433″)Threaded
JSO-1615-03-L16.00mm (0.630″)Threaded

FPGA Bank Connections

Mezzanine connectors MC1, MC2, and MC3 are high-density connectors providing access to power, fabric I/O, transceivers, and several other signals. Pin mappings are listed on the Pins page linked above. For more details about specific FPGA inputs and outputs, see the Kintex UltraScale documentation.

MC1 and MC2 are 180-pin connectors providing access to fabric I/O and several on-board power supplies, including user-adjustable I/O supply nets VIO1 (MC1) and VIO2 (MC2). MC1 also provides access to FPGA JTAG signals and the I2C interface used for SYZYGY SmartVIO applications.

MC3 is a 120-pin connector with differential pair spacing. This connector provides access to the GTH transceivers on the FPGA.

FPGA BANKHR / HPVOLTAGE RANGE(*)MCXVIOVREFI/O AVAILABLE
46HP0.95 – 1.89 VMC1VIO1VREF152 (including 4 GC pairs)
47HP0.95 – 1.89 VMC1VIO1VREF152 (including 4 GC pairs)
48HP0.95 – 1.89 VMC1VIO1VREF152 (including 4 GC pairs)
24HP0.95 – 1.89 VMC2VIO2VREF252 (including 4 GC pairs)
25HP0.95 – 1.89 VMC2VIO2VREF252 (including 4 GC pairs)
44HP0.95 – 1.89 VMC2VIO2VREF220
45HP0.95 – 1.89 VMC2VIO2VREF252 (including 4 GC pairs)

(*) – Note: Voltage ranges specified here are the range supported by the FPGA bank itself, not the range of the power supply connected to the bank. For power supply ranges refer to Device Settings.

Setting the Adjustable I/O Voltages

A TPS65400 high-efficiency switching regulator on the XEM8350 provides two adjustable bank voltages VIO1 and VIO2. These are connected to the FPGA bank VCCIO according to the tables above. Please see the Device Settings page for information on configuring these voltages.

For modes that read settings from an IPMI EEPROM on the peripheral, the XEM8350 expects to find this EEPROM at I2C address 0xA2 1010 001x.

Note: Changes to Vadj settings require a power cycle to take effect.

Connector Mating

The three connectors on the XEM8350 are high-density, precision connectors and require considerable forces for mating and un-mating.  To prevent damage to the carrier or peripheral boards, jack screw mounting hardware is used. Please review and follow the Jack Screw Instructions when mating and un-mating.

SYSMON

The Xilinx Kintex UltraScale SYSMON ADC input feature is routed through two 1-kΩ resistors to the MC2 connector. There is a 0.01 µF capacitor installed across the two FPGA pins for decoupling.

FPGA FUNCTIONFPGA PINMC1 PINRESISTOR REFDES
ADC_VN_0AA1516R67
ADC_VP_0Y1614R66

Considerations for Differential Signals

The XEM8350 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs.  Please refer to the Xilinx Kintex UltraScale datasheet for details on using differential I/O standards with the Kintex UltraScale FPGA.

FPGA I/O Bank Voltages

In order to use differential I/O standards with the Kintex UltraScale, you must set the VCCO voltages for the banks in use to the correct voltage according to the Xilinx Kintex UltraScale datasheet.  Please see the section above entitled “Setting the Adjustable I/O Voltages” for details.

Characteristic Impedance

The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.

Differential Pair Lengths

In many cases, it is desirable that the route lengths of a differential pair be matched within some specification.  Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.

Reference Voltage Pins (Vref)

The Xilinx Kintex UltraScale supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM8350 supports these Vref applications for banks 24, 25, 44, 45, 46, 47, and 48. Please see the Xilinx Kintex UltraScale documentation for more details. In summary,

FPGA BANKVADJFPGA PINSMCX PINNOTES
24, 25, 44, 45VIO2AD28, AJ34, AD24, AD23MC2:1The VREF pins for all banks powered by VIO2 are connected together to connector MC2 pin 1.
46, 47, 48VIO1L34, T30, T24MC1:178The VREF pins for all banks powered by VIO1 are connected together to connector MC1 pin 178.

I/O State at Power On

Xilinx Kintex UltraScale FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the XEM8350 holds the PUDC_B pin high with a 1kΩ resistor at R68, disabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 0Ω resistor at R71 and removing the 1kΩ resistor at R68, forcing the PUDC_B pin low.