Simple Pin I/O

The SetWireInValue() and GetWireOutValue() methods in the FrontPanel class allow you to set and get individual pin values across the entire defined Wire address space (0x00-0x1F for WireIn, 0x20-0x3F for WireOut). You can set the WireIn values by passing in the address of the WireIn and its new value. You can read individual WireOut values by passing the address of the WireOut and a bit mask to extract only the relevant bits. After setting a wire in value and before reading a wire out value, remember to update the WireIns and WireOuts, respectively. Otherwise, the values will not be accurate.

C/C++

  OpalKelly::FrontPanelDevices devices;
  UINT32 A;

  auto dev = devices.Open();
  dev->ConfigureFPGA("example.bit");

  OpalKelly::FPGADataPortClassic* dp;
  if (dev->GetFPGADataPortClassic(dp) != okErrorCode::NoError) {
      std::cerr << "Failed to get FPGA Data Port Classic.\n";
      return;
  }

  // Send value 0x0A to Wire endpoint with address 0x03
  dp->SetWireInValue(0x03, 0x0A);
  dp->UpdateWireIns();

  // Retrieve value on Wire endpoint with address 0x20
  dp->UpdateWireOuts();
  A = dp->GetWireOutValue(0x20);Code language: PHP (php)

C#

  okCFrontPanelDevices devices = new okCFrontPanelDevices();
  UInt32 A;

  okCFrontPanel dev = devices.Open("");
  dev.ConfigureFPGA("example.bit");

  okCFPGADataPortClassic dp = dev.GetFPGADataPortClassic();
  if (dp == null) {
      Console.Error.WriteLine("Failed to get FPGA Data Port Classic.");
      return;
  }

  // Send value 0x0A to Wire endpoint with address 0x03
  dp.SetWireInValue(0x03, 0x0A);
  dp.UpdateWireIns();

  // Retrieve value on Wire endpoint with address 0x20
  dp.UpdateWireOuts();
  A = dp.GetWireOutValue(0x20);Code language: JavaScript (javascript)

Python

  devices = ok.FrontPanelDevices()

  dev = devices.Open()
  dev.ConfigureFPGA("example.bit")

  dp = dev.GetFPGADataPortClassic()
  if dp is None:
      print("Failed to get FPGA Data Port Classic.")
      sys.exit(1)

  # Send value 0x0A to Wire endpoint with address 0x03
  dp.SetWireInValue(0x03, 0x0A)
  dp.UpdateWireIns()

  # Retrieve value on Wire endpoint with address 0x20
  dp.UpdateWireOuts()
  A = dp.GetWireOutValue(0x20)Code language: Python (python)

Java

  public class Example {
      okCFrontPanelDevices devices;
      okCFrontPanel dev;
      okCFPGADataPortClassic dp;
      long A;
      okCFrontPanel.ErrorCode error;

      public void Initialize() {
          devices = new okCFrontPanelDevices();
          dev = devices.Open("");
          error = dev.ConfigureFPGA("example.bit");
          // It's a good idea to check for errors here!
          dp = dev.GetFPGADataPortClassic();
          if (dp == null) {
              System.err.println("Failed to get FPGA Data Port Classic.");
              return;
          }
      }

      public void SetPinValues() {
          // Send value 0x0A to Wire endpoint with address 0x03
          dp.SetWireInValue(0x03, 0x0A);
          dp.UpdateWireIns();
      }

      public long GetPinValues() {
          // Retrieve value on Wire endpoint with address 0x20
          dp.UpdateWireOuts();
          A = dp.GetWireOutValue(0x20);
          return A;
      }
  }Code language: PHP (php)

JavaScript

const deviceManager = window.FrontPanelAPI.deviceManager;
const dev = await deviceManager.openDevice("");

const fpgaConfig = dev.getFPGAConfiguration();
await fpgaConfig.loadConfigurationFromFile("example.bit");

const fpgaDataPort = await dev.getFPGADataPortClassic();

// Send value 0x0A to Wire endpoint with address 0x03
fpgaDataPort.setWireInValue(0x03, 0x0A, 0xff);
await fpgaDataPort.updateWireIns();
 
// Retrieve value on Wire endpoint with address 0x20
await fpgaDataPort.updateWireOuts();
const A = fpgaDataPort.getWireOutValue(0x20);Code language: JavaScript (javascript)

Verilog

// FrontPanel module instantiation
okWireIn inA(
     .ok1(ok1),
     .ep_addr(8'h03),
     .ep_dataout (dataA)
);
 
okWireOut outA(
     .ok1(ok1),
     .ok2(ok2x[0*17 +: 17]),
     .ep_addr (8'h20),
     .ep_datain (dataA)
);Code language: Verilog (verilog)

VHDL

-- FrontPanel module instantiations
inA  : okWireIn port map(
     ok1=>ok1,
     ep_addr=>x"03",
     ep_dataout=>dataA
);
 
outA : okWireOut port map(
     ok1=>ok1,
     ok2=>ok2s( 1*17-1 downto 0*17 ),
     ep_addr=>x"20",
     ep_datain=>dataA
);Code language: VHDL (vhdl)