A FrontPanel Platform GUI enables users to generate and view signals with multiple frequency vectors using the SZG-DAC-AD9116 and the SZG-ADC-LTC226x on an XEM8320-AU25P. The FrontPanel Subsystem Vivado IP Core stimulates our HLS Fast Fourier Transform (FFT) cores to combine and convert these vectors into a time domain digital output signal and vice versa.

This sample paired with an Opal Kelly FPGA Development or Integration module provides a great starting template for those interested in DSP applications. The sample can be enhanced by additional DSP processing through additional user defined AMD-Xilinx’s HLS cores, or through AMD-Xilinx’s Filter, Modulation, Trig Functions, etc. DSP IP Cores.

We currently have simpler ADC and DAC example designs available on our open source Github that target the XEM7320 and the XEM8320. Note, these are no longer supported or maintained.

The ADC design is a simple scope that uses Python to display the signals from the ADC. More information is available in the READMEs for the desired XEM module.

The DAC design features AM/FM modulation and can pipe audio into the design to modulate it over a carrier wave with the requested parameters. You can learn more about it on our blog, here.

• GitHub: Opal Kelly’s HLS Fast Fourier Transform (FFT) Core
  A synthesizable and scalable pipelined fixed-point Decimation-in-Frequency FFT and IFFT FPGA library for use with AMD-Xilinx’s High Level Synthesis (HLS).
  
• Github: FFTScope Example Design
  A complete sample using HLS FFT and IFFT cores. This sample targets the XEM8320, SZG-DAC-AD9116, and SZG-ADC-LTC226x.
  

Users will learn the following:

1. Set up and use a FrontPanel Platform GUI for control of FrontPanel-enabled gateware.
2. Utilize the open-source JavaScript library Chart.js for data acquisition and oscilloscope display.
3. Create IPI Block Designer projects utilizing the FrontPanel Subsystem Vivado IP Core.
4. Get introduced to a workflow that incorporates FrontPanel and AMD-Xilinx’s High Level Synthesis (HLS) components.

• Hardware
  • XEM8320-AU25P
  • SZG-DAC-AD9116 on Port A
  • SZG-ADC-LTC226x on Port B
    • Only required for FrontPanel Platform Signal Generator + Spectrum Analyzer application
• Software
  Two applications are available as options for interfacing with the design:
  • FFTScope Github release
    • FFTScope-ExampleDesign-ADC-1X-v3.1.asar
      • Select the FFTScope-ExampleDesign-ADC-12-v3.1.asar for the SZG-ADC-LTC2264-12
      • Select the FFTScope-ExampleDesign-ADC-14-v3.1.asar for the SZG-ADC-LTC2268-14
    • FrontPanel v6.0.0 (beta) or later

The goal of this tutorial is to use the provided prebuilt ASAR in-hardware to generate a four-tone signal and verify the time and frequency domain characteristics of the signal.

The Signal Generator component of the user interface will be used to configure the IFFT to produce the signal that is output through the SZG-DAC-AD9116. The signal will be routed to the SZG-ADC-LTC226x and the FFT to produce time and frequency domain plots.

1. Power off the XEM8320-AU25P.
2. Connect a SZG-DAC-AD9116 to port A on the XEM8320-AU25P.
3. Connect a SZG-ADC-LTC226x to port B on the XEM8320-AU25P.
4. Connect one of the outputs of the SZG-DAC-AD9116 to one of the inputs of the SZG-ADC-LTC226x.
5. Power on the XEM8320-AU25P using a 12-volt supply.
6. Connect the XEM8320-AU25P to a PC using a USB-C cable.

1. Open the FrontPanel Platform application.
2. Install the FFTScope app by clicking the ‘+’ button in the Installed Applications panel. Then locate the FFTScope-ExampleDesign-ADC-1X-v3.1.asar file you downloaded. For more details, see Building the Template App Guide.
3. Click and drag the FFTScope Application card to the available XEM8320 device.

1. Enable Auto Scaling.
2. Enable the first four frequency vectors.
3. Set the first frequency vector to bin number 199 and -1 dBFS.
4. Set the second fequency vector to bin number 287 and -7 dBFS.
5. Set the third frequency vector to bin number 246 and -28 dBFS.
6. Set the fourth frequency vector to bin number 39 and 0 dBFS.
7. The Time Domain chart should show the waveform of four-tone signal.
8. The Spectrum chart should show the frequency domain representation of the four-tone signal.

We provide various build scripts for instructing Vitis HLS to build our FFT core, creating the Vivado project, configuring the required IP Cores, and constructing the IPI Block Design Project. The end result of this How-To is the construction of the following Vivado IPI Block Design project:

This design requires the following to build:

• Vitis HLS
  Notice: Our supported version is v2023.2. Versions outside of this are not guaranteed to be maintained.
• Vivado
  Notice: Our supported version is v2023.2. Versions outside of this are not guaranteed to be maintained.
• Vivado IP Cores’ Distribution v1.0.2 or later
• XEM8320-AU25P Board file v1.2 or later 
• Latest FFTScope-ExampleDesign-vX.Y release Source Code (zip or tar.gz)

Windows

1. Follow How-To Install for the XEM8320-AU25P’s Board file v1.2 or later.
2. Follow Add IP Cores’ Distribution to Vivado for Vivado IP Cores’ Distribution v1.0.2 or later. The location you installed this Distribution to will be used in step 6.
3. Extract the sample’s release’s Source Code (zip or tar.gz).
4. Open a command prompt and cd to the FFTScope example folder.
   cd C:/pathToDownload/FFTScope
   Note: PowerShell won’t work, Command Prompt must be used.
5. Run the settings64.bat file in the Vitis HLS and Vivado installation directories.
   path/to/vitis/2023.2/settings64.bat
path/to/vivado/2023.2/settings64.bat
6. Run the appropriate .bat file for your SZG-ADC-LTC226x target:
   – For SZG-ADC-LTC2264-12, use windows_create_project-adc-12.bat.
   – For SZG-ADC-LTC2264-14, use windows_create_project-adc-14.bat.
   Provide the path to the Vivado IP Cores’ Distribution as an argument:
   windows_create_project-adc-12.bat C:/pathToDownload/FrontPanel-Vivado-IP-Dist-vX.Y.Z

Linux

1. Follow How-To Install for the XEM8320-AU25P’s Board file v1.2 or later.
2. Follow Add IP Cores’ Distribution to Vivado for Vivado IP Cores’ Distribution v1.0.2 or later. The location you installed this Distribution to will be used in step 6.
3. Extract the sample’s release’s Source Code (zip or tar.gz).
4. Open a terminal and cd to the FFTScope example folder.
   cd C:/pathToDownload/FFTScope
5. Run the settings64.sh files in the Vitis HLS and Vivado installation directories.
   source path/to/vitis/2023.2/settings64.sh
source path/to/vivado/2023.2/settings64.sh
6. Run the appropriate .bat file for your SZG-ADC-LTC226x target:
   – For SZG-ADC-LTC2264-12, use linux_create_project-adc-12.bat.
   – For SZG-ADC-LTC2264-14, use linux_create_project-adc-14.bat.
   Provide the path to the Vivado IP Cores’ Distribution as an argument:
   linux_create_project-adc-12.bat C:/pathToDownload/FrontPanel-Vivado-IP-Dist-vX.Y.Z

We utilize the Behavioral Simulation features of the FrontPanel Subsystem Vivado IP Core to provide a simulation of the design. The end result of this How-To is the creation of a simulation waveform for a two-tone wave with simulated PipeOut reads of the FFT calculations:

1. Follow How-To Setup the Project
2. In Vivado, launch Flow>Run Simulation>Run Behavioral Simulation
3. Launch Run>Run All

1. Follow How-To Setup the Project
2. In Vivado, launch Flow>Generate Bitfile

• Latest FFTScope-ExampleDesign-vX.Y release Source Code (zip or tar.gz)
• Install prerequisites from the Building the Template App
• FrontPanel 6.0.0 installed

1. Extract the sample’s release’s Source Code (zip or tar.gz).
2. cd to the Platform folder:
   cd C:/pathToDownload/FFTScope/Software
3. Place the prebuilt bitfile for your SZG-ADC provided in the Github Release in the assets folder
   • FFTScope-ExampleDesign-ADC-12.bit or FFTScope-ExampleDesign-ADC-14.bit
4. Ensure the program will use the correct bitfile by changing which line is commented out on this line in src/App.tsx:
   • 
   • I.e., if you are using the SZG-ADC-LTC2264-12, uncomment line 92 and comment out line 93.
5. Install the dependencies:
   npm install
6. Build the application:
   npm run pack
7. Open the FrontPanel Platform application and install the output package (output/app.asar) using the app launcher. See: Building the Template App for more details.
8. Run the application by clicking and dragging the FFTScope app card to the available XEM8320 device.

Below we define terms and three important data flow stages for this sample:

• Frequency Domain BRAM – Contains the 256 frequency domain vectors the FFT computes with.
• IFFT Start – The FrontPanel Platform application communicate with the FrontPanel Subsystem Vivado IP Core generated FrontPanel HDL endpoints to store the Vector Set into the Frequency Domain BRAM. A custom RTL Slicer is used to distribute control signals throughout the design.
• FFT Enable – Enables the FFT core to calculate the SZG-ADC input.

The components of this panel are used to control the output of the DAC.

• Add Tone – This appends a new frequency vector component to the list.
• Autoscale – If enabled, will scale the output signal so that it does not exceed the maximum in order to prevent clipping.
• Frequency Vector
  • Bin Slider – This sets the frequency bin number used to configure the IFFT.
  • Frequency (kHz) – The frequency corresponding to the bin number selected.
  • Magnitude (dBFS) – DeciBel Full Scale. 0 = full power, -120 = nearly off.
  • Enabled – If checked, the frequency vector will be included when computing the output signal.
  • X – Removes the frequency vector component from the list.
• Reset – Resets the signal generator components of the design.

The components of these panels are used to retrieve and visualize the input of the ADC.

• Continuous – If enabled, will continuously retrieve frames of 1,024 samples acquired from the ADC.
• Sample – Retrieves a single frame of 1,024 samples acquired from the ADC.
• Reset – Resets the data acquisition components of the design.
• Time Domain Chart – Displays a frame of 1,024 samples retrieved for each of two separate channels.
• Spectrum Chart – Displays the results retrieved from the FFT corresponding to the samples acquired from the ADC.

Our supported releases for the FFT Signal Generator sample are located on GitHub at:
opalkelly-opensource/FFTScope

• Name change
• Moved to separate GitHub repository

• Updated to provide application information

• Updated to use version 0.5.0 of the FrontPanel Platform API
• Updated so application can be installed in the FrontPanel Platform launcher

• FrontPanel Platform Beta GUI updates
• Bitfiles are included in the ASAR file.

• Renamed design
• Added ADC + IFFT functionality
• FrontPanel Alloy GUI functionality

• Initial Creation
• Bitfile generated using the following tool versions:
  Vivado v2022.1
  Vitis HLS v2022.1
  Vivado IP Cores’ Distribution v1.0.2
  XEM8320-AU25P Board file v1.2