The Counters example is a bit more complicated than the simple example. It includes a few more FrontPanel components and also adds a few Trigger endpoints.  More importantly, though, it adds more hardware in the form of HDL so you can see how FrontPanel integrates with HDL in a slightly more complicated setup.

The FrontPanel Platform interface for this example is shown below

The hardware for the Counters example has two counters, the okHostInterface, a single Wire In endpoint, three Wire Out endpoints, a Trigger In endpoint, and two Trigger Out endpoints. The hardware also routes to the LEDs on the XEM3001.

The first counter is an 8-bit up counter with enable, synchronous reset, disable, and two triggers. The enable signal is generated by a separate 24-bit counter to make the count progression slower. The Verilog HDL for this counter and its clock divider counter is shown here:

always @(posedge sys_clk) begin
   div1 <= div1 - 1;
   if (div1 == 24'h000000) begin
      div1 <= 24'h400000;
      clk1div <= 1'b1;
   end else begin
      clk1div <= 1'b0;
   end
   
   if (clk1div == 1'b1) begin
      if (reset1 == 1'b1)
         count1 <= 8'h00;
      else if (disable1 == 1'b0)
         count1 <= count1 + 1;
      end

   if (count1 == 8'h00)
      count1eq00 <= 1'b1;
   else
      count1eq00 <= 1'b0;

   if (count1 == 8'h80)
      count1eq80 <= 1'b1;
   else
      count1eq80 <= 1'b0;
endCode language: PHP (php)

From the description, we gather that when RESET1 is asserted, the counter will hold the value 0x00. When DISABLE1 is asserted, the counter holds its current value. Otherwise, the counter will increment each time the clock divider counter expires. We also see that COUNT1EQ00 and COUNT1EQ80 are asserted when the counter is 0x00 or 0x80 respectively.

Note that this counter operates on CLK1 which is mapped to LCLK1 on the PLL.

The second counter operates on CLK2 which is mapped to LCLK2 on the PLL. Using the PLL Configuration Dialog, we will be able to observe the effects of changing the PLL frequencies on the two counters.

The Verilog HDL for this counter and its own divider is listed below. This counter will count up when UP2 is asserted, count down when DOWN2 is asserted, and automatically count up when AUTOCOUNT2 is asserted. Note that UP2 and DOWN2 must be asserted for exactly one CLK2 cycle for the counter to count only one.  This is why we have the Trigger endpoints.

always @(posedge sys_clk) begin
   div2 <= div2 - 1;
   if (div2 == 24'h000000) begin
      div2 <= 24'h100000;
      clk2div <= 1'b1;
   end else begin
      clk2div <= 1'b0;
   end
   
   if (reset2 == 1'b1)
      count2 <= 8'h00;
   else if (up2 == 1'b1)
      count2 <= count2 + 1;
   else if (down2 == 1'b1)
      count2 <= count2 - 1;
   else if ((autocount2 == 1'b1) && (clk2div == 1'b1))
      count2 <= count2 + 1;

   if (count2 == 8'hff)
      count2eqFF <= 1'b1;
   else
      count2eqFF <= 1'b0;
endCode language: PHP (php)

This example uses several endpoints to provide controllable inputs to the hardware and observable outputs to FrontPanel.  To reduce the number of endpoints, we have chosen to share them among the counters.

The only Wire In endpoint is used to carry the RESET1, DISABLE1, and AUTOCOUNT2 signals. These are wires because we want them to have a static state rather than one-shot signals.

The only Trigger In endpoint is used for the Counter #2 inputs. These are triggers because we want single events (one-shots) to occur, such as a count-up event.

Note that RESET2 behaves the same as RESET1 but we want to have RESET2 behave as a one-shot event so that the user cannot hold RESET2 asserted. Therefore, we attach this one to a Trigger.

These wires provide observables for FrontPanel. They are connected as follows:

This Trigger Out endpoint corresponds to the Counter #1 value. These are triggers because we want these events to update the FrontPanel application.

This Trigger Out endpoint corresponds to the Counter #2 value.