This technical reference covers both the FrontPanel Subsystem and LEDs Vivado IP cores. The IP Cores’ configuration parameters are used when generating the IP Cores’ output products. The IP Cores’ parameters are validated to ensure they conform to the requirements specified in tables 3.1, 3.2, and 3.3.

The parameters can be set through TCL using the following command structure:

set_property -dict [list CONFIG.<Param Name> {<value>} <Additional Param/value pairs>] [get_ips <IP Instance>]Code language: HTML, XML (xml)

For example:

set_property -dict [list CONFIG.BOARD {XEM8320-AU25P} CONFIG.WI.COUNT {1} CONFIG.WI.ADDR_0 {0x08}] [get_ips frontpanel_example]Code language: CSS (css)

Currently, the XEM8350 is the only device to support a secondary Host Interface. Devices supporting the secondary Host Interface provide additional parameters by prepending an “S” field onto their counterparts laid out in Table 3.1. These parameters have identical functionality and the same validation/conformity rules as their counterparts. For brevity, these parameters are removed from Table 3.1:

• S.<type>.COUNT
• S.<type>.ADDR_<31-0>
• S.RB.EN

Additionally, S.EN is used to enable the secondary host interface and is listed in Table 3.1.

The parameters are categorized into the Types defined below:

Notes:

1. The included address bins start at <type>.ADDR_0 through to the <type>.COUNT specified, i.e., a <type>.COUNT of 3 will generate endpoints for the addresses in bins <type>.ADDR_0 through <type>.ADDR_2.
2. PI & BTPI Endpoint types share the same address space. Their summed COUNTs cannot exceed 32, i.e. PI.COUNT + BTPI.COUNT ≤ 32.
3. PO & BTPO Endpoint types share the same address space. Their summed COUNTs cannot exceed 32, i.e. PO.COUNT + BTPO.COUNT ≤ 32.
4. Addresses must be in HEX format, i.e., 0x04. 
5. No two Endpoint address bins can have the same address.
6. Only supported on boards with FPGA Flash.
7. Not intended outside of the GUI flow.
8. Does NOT provide utility in applying board interface constraints as seen in Xilinx provided IP Cores. IP Core automatically applies board constraints through other means.
9. Internal Parameter is automatically configured appropriately based on User parameter types.

Notes:

1. Used for boards whose LEDs are connected to a variable bank voltage controlled by VIO.

For the selected BOARD parameter, the IP Core will check the project’s currently configured FPGA part. If it does not match the associated FPGA part displayed in the table below, referred to as the “Enforced FPGA Part,” the IP Core will restrict generation until the issue is resolved.