In this tutorial, we introduced the IP Core’s test bench template and how to utilize it to quickly set up behavioral simulations of FrontPanel enabled digital designs. First, we configure the FrontPanel Subsystem Vivado IP Core with WireIn and TriggerIn Endpoints and stimulate those Endpoints using the FrontPanel API calls that are available in the Host Simulation Library. Lastly, we introduce the LFSR Simulation Example Design, which is a complete example that utilizes all Endpoint types in a larger design.

This tutorial assumes familiarity with our Host Simulation HDL. 

1. Add IP Cores’ Distribution to Vivado.
2. Create an IP Core Compatible Vivado Project.

1. On the Endpoints page:
   1. Enter a count of “1” for both the WireIn and TriggerIn endpoint types. 
   2. For the WireIn endpoint, enter an address of 0x13.
   3. For the TriggerIn endpoint, enter an address of 0x48.
2. Click OK.
3. When prompted to Generate Output Products, select Generate.

1. Create a new top level test bench file in the Simulation file group.
2. Locate test_bench_template.v under the Test Bench folder in the IP Sources panel. If using the Block Designer, it is located under the Simulation sources for the IP Core. Copy the contents of this file into the newly created top level test bench file.
3. Obtain the instance of the IP Core’s instantiation template under the Instantiation Template folder of the IP Sources panel.

1. Substitute the top level module instantiation in the copy of test_bench_template.v with the instantiation retrieved from the IP Core’s Instantiation Template:

wire okClk;
wire [31:0] wi13_ep_dataout;
wire [31:0] ti48_ep_trigger;
wire ti48_ep_clk;

assign ti48_ep_clk = okClk;

frontpanel_0 simulation_example (
  .okUH(okUH),                        // input wire [4 : 0] okUH
  .okHU(okHU),                        // output wire [2 : 0] okHU
  .okUHU(okUHU),                      // inout wire [31 : 0] okUHU
  .okAA(okAA),                        // inout wire okAA
  .okClk(okClk),                      // output wire okClk
  .wi13_ep_dataout(wi13_ep_dataout),  // output wire [31 : 0] wi13_ep_dataout
  .ti48_ep_trigger(ti48_ep_trigger),  // output wire [31 : 0] ti48_ep_trigger
  .ti48_ep_clk(ti48_ep_clk)           // input wire ti48_ep_clk
);Code language: JavaScript (javascript)

2. Substitute the template copy’s example Host Simulation Library API calls in the Initial block at the bottom of the template with:

initial begin
    FrontPanelReset;

    SetWireInValue(8'h13, 32'hdead_beef, NO_MASK);
    UpdateWireIns;

    ActivateTriggerIn(8'h48, 7);
end
Code language: PHP (php)

1. In Vivado, click Flow > Run Simulation > Run Behavioral Simulation
2. In the WaveForm Viewer, notice the following:
   1. wi13_ep_dataout[31:0] net set to 0xdeadbeef.
   2. ti48_ep_trigger[31:0] net received a one clock cycle pulse (okClk) on bit 7.

For a complete simulation example that utilizes all Endpoint types in a larger design, open the LFSR Simulation Example Design. See the Example Designs Getting Started tutorial for instructions on opening this example design.