The Preferences dialog (shown below) can be shown by navigating under the FrontPanel menu FrontPanel → Preferences…

Wire Out and Trigger Out endpoints are updated using timed polling by the FrontPanel software.  This update rate is determined by your design’s needs (how quickly you need to see wire changes) as well as the performance of your PC.  On an Athlon 2100+, even the fastest update rate places minimal (<2%) load on the CPU.

This is only applicable to legacy products that use a CY22150 or CY22393 PLL.

This option determines whether an FPGA download configures the PLL prior to download.  In most cases, this is the desired behavior so that a valid clock is available when the FPGA comes out of the configuration state.  Sometimes, however, you may want to keep the current PLL settings in effect and not update the EEPROM.

When unchecked, each FrontPanel “panel” is displayed in a toolbox window which does not register with the taskbar.  When checked, these panels will register with the taskbar so that you can easily select a particular panel.

Asynchronous transfers allow USB transfer requests to be queued and sequenced by the operating system.  This decreases software overhead and increases overall throughput.  However, many Windows 2000-based machines have problems with asynchronous transfers and may not communicate with the FPGA properly when this feature is enabled.

You may find that you need to disable asynchronous transfers before any FPGA communication.  Otherwise, the communication link may become “tainted” and will not work.  Therefore, if you experience problems with Windows 2000 and FrontPanel communication, we advise that you disable asynchronous transfers before communicating with your board.

From within your own software, there is an API method to control this feature.

Change FrontPanel’s appearance to be light mode, dark mode, or set to the system’s preference.