To download an FPGA configuration file to the target device, simply click on the icon shown to the left.   A file selector dialog will appear from which you can choose the Xilinx bitfile (*.bit) or Altera raw biftile (*.rbf) to download.  If you accept the file, the download will proceed immediately.  The following procedure is run when you configure the device:

1. The on-board PLL is configured with the parameters stored in EEPROM. (if supported by the module)
2. The FPGA is reset and a programming sequence is initiated.
3. The configuration data is downloaded to the FPGA.
4. The FPGA is checked to verify that the configuration was successful (DONE is asserted).
5. The Reset Profile is performed. (if supported by the module)

Once complete, the FPGA is now configured and “running” with the new design.

As an alternative to clicking the download icon and using a file selector to choose the configuration file, you can simply drag a Xilinx bitfile or Altera raw bitfile onto the icon and release it.  FrontPanel then proceeds as if you had just chosen the file in the file selector.