Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM8350 may be found at the link to the right.

A small 2-pin connector (Molex 53398-0271) at J4 provides power to an optional fansink for FPGA cooling. This fan is controlled by a digital fan controller as part of the Device Sensors and Device Settings capabilities. Please see the Device Settings section for details on controlling the fan.

The fansink is powered directly by the +VDCIN input voltage to the XEM8350. The allowable range for +VDCIN is 5-16 VDC. When utilizing the Opal Kelly FANSINK-40X40, it is recommended to use an input voltage within the specified operating range of the fansink: 6-13.8 VDC.

Two high-density, 180-pin expansion connectors are available on the bottom-side of the XEM8350 PCB. A third high data rate optimized 120-pin expansion connector is provided on the bottom-side of the XEM8350 PCB. These expansion connectors provide user access to several power rails on the XEM8350, the JTAG interface on the FPGA, and 332 dedicated I/O pins on the FPGA, including several global clock inputs. High-speed gigabit transceiver signals are also available through these expansion connectors. Each connector has a ground spine running its entire length for a solid reference ground connection.

The MC1 and MC2 connectors on the XEM8350 are Samtec part number: QSH-090-01-L-D-A. The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-090-01-F-D-A part is used on the BRK8350 breakout board.

The MC3 connector on the XEM8350 is Samtec part number: QSH-060-01-L-D-DP-A. This connector has more isolation space between the differential pairs of the transceiver pins. The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-060-01-L-D-DP-A part is used on the BRK8350 breakout board.

The XEM8350 uses Samtec Jack Screw Standoffs to ensure even mounting and un-mounting pressure when connecting to a base board. The table below lists the appropriate Samtec Jack Screw Standoffs along with the total mated height. The JSO-0515-01 part is used on the BRK8350 breakout board. Samtec Jack Screw Standoffs are sold as a set consisting of the base, jack screw, washer, and mounting screw. Four Jack Screw Standoffs are required to mount the XEM8350 to a base board.

Mezzanine connectors MC1, MC2, and MC3 are high-density connectors providing access to power, fabric I/O, transceivers, and several other signals. Pin mappings are listed on the Pins page. I/O and transceiver signals from the FPGA are directly connected to the mezzanine connectors, with the exception of the transceiver refclocks which are AC coupled. For more details about specific FPGA inputs and outputs, see the Kintex UltraScale documentation.

MC1 and MC2 are 180-pin connectors providing access to fabric I/O and several on-board power supplies, including user-adjustable I/O supply nets VIO1 (MC1) and VIO2 (MC2). MC1 also provides access to FPGA JTAG signals and the I2C interface used for SYZYGY SmartVIO applications.

MC3 is a 120-pin connector with differential pair spacing. This connector provides access to the GTH transceivers on the FPGA.

Two programmable high-efficiency switching regulators are on the XEM8350 which control the two adjustable voltages VIO1 and VIO2. These are connected to the FPGA bank VCCIO according to the tables above. There are two ways to set these voltages:

• Device Settings – The FrontPanel firmware supports separate non-volatile device settings that are used to set these voltages during the power-on sequence. You can manually program these using the FrontPanel API or the FrontPanel application. See the Device Settings page for information on configuring these voltages.
• Peripheral Personality EEPROM – You can program a small EEPROM on your peripheral (the device that attaches to the XEM8350 mezzanine connectors) that can tell the FrontPanel firmware how to configure these voltages during the power-on sequence. See below for additional information.

Note: Changes to VIO settings require a power cycle to take effect.

During power-on sequencing the device firmware will query an I²C EEPROM at address 0xA2 1010 001x. This EEPROM would be connected to SUPPLY_SDA (MC1 pin 10) and SUPPLY_SCL (MC1 pin 12) and uses 3.3V logic levels. If present, the firmware will attempt to read an IPMI-formatted block of data that tells it how to configure the three adjustable voltage regulators.

Opal Kelly has provided an online tool to generate the contents of this EEPROM. Simply enter the details of your product into the online form to generate a binary file that can be stored on your EEPROM. The FrontPanel application can be used to program the generated binary file into the EEPROM.

The three connectors on the XEM8350 are high-density, precision connectors and require considerable forces for mating and un-mating. To prevent damage to the carrier or peripheral boards, jack screw mounting hardware is used. Please review and follow the Jack Screw Instructions when mating and un-mating.

The Xilinx Kintex UltraScale SYSMON ADC input feature is routed through two 100-Ω resistors to the MC1 connector. There is a 2.2 nF capacitor installed across the two FPGA pins for decoupling.

The XEM8350 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs. Please refer to the Xilinx Kintex UltraScale datasheet for details on using differential I/O standards with the Kintex UltraScale FPGA.

In order to use differential I/O standards with the Kintex UltraScale, you must set the VCCO voltages for the banks in use to the correct voltage according to the Xilinx Kintex UltraScale datasheet. Please see the section above entitled “Setting the Adjustable I/O Voltages” for details.

The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.

In many cases, it is desirable that the route lengths of a differential pair be matched within some specification. Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.

VBATT is by default connected to ground via R121. It is also connected to MC2 pin 6. For information on using VBATT for encryption key storage see the Encryption Key Storage page.

The Xilinx Kintex UltraScale supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM8350 supports these Vref applications for banks 24, 25, 44, 45, 46, 47, and 48. Please see the Xilinx Kintex UltraScale documentation for more details. In summary,

Xilinx Kintex UltraScale FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the XEM8350 holds the PUDC_B pin high with a 1kΩ resistor at R68, disabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 0Ω resistor at R71 and removing the 1kΩ resistor at R68, forcing the PUDC_B pin low.