This reference design uses FrontPanel with an XEM8320 to obtain data from a SYZYGY ADC peripheral. A host PC running Windows 10 generates an animated graph of the retrieved data. The design is based heavily on Xilinx Application Note 524, XAPP524, and implements a simplified version of the serial LVDS interface described by Xilinx.
This tutorial guides you through using your SZG-ADC-LTC2264-12 or SZG-ADC-LTC2268-14 with this example reference design. You will accomplish building the gateware and running the graphing utility.
- Turn off your XEM8320.
- Connect a SZG-ADC to port A.
- Connect an SMA cable to the SZG-ADC and your analog signal source. An audio source with a voltage less than 2 volts peak-to-peak works well.
- Connect your XEM8320 to your host PC with the provided USB cable.
- Power on your XEM8320.
- Follow the “How to Build the Gateware” section below.
- Follow the “How to Run the Graphing Utility” section below.
How to Build the Gateware
- Open Vivado 2021.1.1 or later.
- In the Tcl Console, enter
cd <ADC_Sample directory>.
- Make sure you use forward slashes instead of backslashes for the file structure.
- If you are using the ADC-LTC2264-12, enter
source project-adc12.tclto generate the project.
- If you are using the ADC-LTC2268-14, enter
source project-adc14.tclto generate the project.
- Add the XEM8320 FrontPanel gateware to the Vivado project.
- This is found in the “FrontPanelHDL/XEM8320-AU25P” folder of the FrontPanel install.
- Click ‘Generate Bitstream’ after the project opens.
How to Run the Graphing Utility
- Set up your Python environment by following the instructions from the Opal Kelly ‘Programming Languages’ documentation’ under ‘Python API,’ placing the required files into the reference design’s
- Place the generated bitstream from ‘How to Build the Gateware’ in the reference design’s
- Power on the XEM8320.
adc_read.pywith the name of the bitfile as an argument.
- The animated graph is now displaying the analog signal.