The Flash memory attached to the USB microcontroller stores device firmware and settings as well as user data that is accessible via the FrontPanel API.  The API includes three methods for accessing this memory: FlashEraseSector, FlashWrite, and FlashRead.  Please refer to the FrontPanel User’s Manual and the FrontPanel API Reference for information about applying these methods.

The Numonyx N25Q128A11B1240E is a 16 MiB Flash memory arranged into 256 64-kiB sectors.  Each sector contains 256 256-byte pages.  Sectors 0…15 are reserved for device firmware and settings and are not accessible to user software.  The remaining 15 MiB may be erased, written, and read using the FrontPanel API at any time even without a valid FPGA configuration.  Full 64 kiB sectors must be erased at a time.  However, contents may be read or written on any page address boundary.

The SPI Flash attached to the FPGA is an ISSI IS25WP256D-JLLE or equivalent.  It provides non-volatile storage for use by the FPGA.

The Flash memory is connected to the FPGA through the configuration bank. The STARTUPE3 Xilinx primitive can be used to interface with the Flash memory from a user design. The flash pins are connected to the configuration according to the table below:

The FPGA Flash may be used to store a Xilinx bitfile to configure the FPGA at power-on. The Flash can be written using FrontPanel or through Vivado with a Xilinx JTAG cable.

FrontPanel can be used to erase and program the power-on bitfile and the Flashloader tool is provided to perform these steps from a simple command-line utility. Source code to the Flashloader tool is included with the FrontPanel SDK installation.

Using FrontPanel’s flash programming utility, apply the following settings:

• Target: FPGA Flash
• Data Type: Configuration
• Start Sector: 0

Using the Flashloader sample, called with a single argument (the filename for a valid Xilinx bitfile), the Flashloader sample will erase the first sectors in the FPGA Flash, then write the bitfile.

An FPGA configuration loaded in the FPGA Flash will always load at power on until the flash memory containing the configuration is cleared.

If you plan to utilize the FPGA Flash for configuring the FPGA at power-on, the Vivado software needs certain details about the FPGA flash to generate a suitable bitfile for this specific configuration mode. This bitfile is subsequently loaded into the FPGA flash. To accomplish this, implement the following XDC constraints within your project.

It is important to understand that if you generate bitfiles with the following constraints, they cannot be loaded through the FPGA Configuration Download feature in the FrontPanel application. Trying to do so will result in an error message stating FPGA configuration failed: Done did not go high.

set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 90 [current_design]Code language: Verilog (verilog)