Getting Started Guide

Configuring a Bitfile

This guide will take you through the process necessary to configure the Programmable Logic (PL) side of the Zynq Ultrascale+ MPSoC from the Processor Side (PS).

The following are requirements for this guide:

  • ECM1900
  • BRK1900
  • microSD card
  • USB type C storage device. Type converting adapter can be used
  • USB type C to Host USB type cable

The following instructions show how to configure a bitfile:

  1. Unplug USB cable from Host PC.
  2. Insert the microSD card containing the BRK1900 Linux image into the microSD card slot on the ECM1900.
  3. Power the BRK1900 either through the DC barrel jack or the 6-pin Mini-Fin connector. Please read and follow the voltage and current specifications located under ‘Powering the BRK1900’ at BRK1900 Breakout Board.
  4. Plug in a USB type C cable from the UART port on the ECM1900 to the USB port of your host computer.
  5. Use your favorite serial console on your host computer to communicate with the COM port your USB device is connected to. The baud rate for this connection is 115200.
  6. Power cycle the BRK1900 to receive console output though the serial connection.
  7. After boot completes you can log in using using the credentials below:
    • Username: root
    • Password: root
  8. Generate a compatible bitfile for the ECM1900 (instructions shown below). You may also use our provided LED-ECM1900.bit which lights up the LEDs as 11000011.
  9. Place the bitfile onto a USB type C storage device.
  10. Plug the storage device into either the USB 3.0 type C port on the BRK1900, or the USB 2.0 type C port on the ECM1900.
  11. The storage device will mount to /run/media/sda1. Run the following command to configure the bitfile onto the PL side.
fpgautil -b /run/media/sda1/LED-ECM1900.bit

Creating a Compatible Bitfile

Required resources:

This guide will take you through generating a compatible bitfile for the ECM1900/BRK1900. Each bitfile generated for the ECM1900/BRK1900 will need the Zynq Ultrascale+ MPSoC IP instantiated within it. This IP will need to be configured with our included preset configuration TCL preset.

  1. Open a new Vivado design which targets the FPGA chip on your ECM1900
  2. Create a new block design in the IP Integrator (IPI)
  3. Instantiate the Zynq UltraScale+ MPSoC IP within the IPI
  4. Open the Zynq UltraScale+ MPSoC IP configuration GUI
  5. Click “Presets”
  6. Click “Apply Configuration”
  7. Select our provided Zynq UltraScale+ MPSoC IP Preset TCL file
  8. Click “OK” in the configuration wizard to save this configuration
  9. Select ‘Generate Block Design’ to generate the Verilog HDL sources
  10. Right click on the generated block design and select “Create HDL Wrapper”
  11. Instantiate the HDL Wrapper into your top level HDL module
  12. Add additional PL resources to your HDL design as required
  13. Generate the BRK1900 bitfile
  14. Configure the bitfile to the ECM/BRK1900 using the instructions provided above in ‘Configuring a Bitfile’