Configuring a Bitfile
This guide will take you through the process necessary to configure the Programmable Logic (PL) side of the Zynq Ultrascale+ MPSoC from the Processor Side (PS).
The following are requirements for this guide:
- microSD card
- USB type C storage device. Type converting adapter can be used
- USB type C to Host USB type cable
The following instructions show how to configure a bitfile:
- Unplug USB cable from Host PC.
- Insert the microSD card containing the BRK1900 Linux image into the microSD card slot on the ECM1900.
- Power the BRK1900 either through the DC barrel jack or the 6-pin Mini-Fin connector. Please read and follow the voltage and current specifications located under ‘Powering the BRK1900’ at BRK1900 Breakout Board.
- Turn on the BRK1900.
- Plug in a USB type C cable from the UART port on the ECM1900 to the USB port of your host computer.
- Use your favorite serial console on your host computer to communicate with the COM port your USB device is connected to. The baud rate for this connection is 115200.
- Power cycle the BRK1900 to receive console output though the serial connection.
- After boot completes you can log in using using the credentials below:
- Username: root
- Password: root
- Generate a compatible bitfile for the ECM1900 (instructions shown below). You may also use our provided LED-ECM1900.bit which lights up the LEDs as 11000011.
- Place the bitfile onto a USB type C storage device.
- Plug the storage device into either the USB 3.0 type C port on the BRK1900, or the USB 2.0 type C port on the ECM1900.
- The storage device will mount to /run/media/sda1. Run the following command to configure the bitfile onto the PL side.
fpgautil -b /run/media/sda1/LED-ECM1900.bit
Creating a Compatible Bitfile
This guide will take you through generating a compatible bitfIle for the ECM1900. Each bitfile generated for the ECM1900/BRK1900 will need the Zynq Ultrascale+ MPSoC IP instantiated within it. This IP will need to be configured with our included preset configuration TCL script located at the following GitHub repository: opalkelly-opensource/ecm1900-tools.
- Update your local board files to include the BRK1900 from the Xilinx BoardStore.
- Open a new Vivado design to target the BRK1900 board.
- Create a new block design in the IP Integrator (IPI).
- Instantiate the Zynq UltraScale+ MPSoC IP within the IPI.
- Click on the “Run Block Automation” notification and apply the “Board Preset” to this IP.
- Select ‘Generate Block Design’ to generate the Verilog HDL sources.
- Instantiate this generated block design into your top level HDL module.
- Add additional PL resources to your HDL design as required.
- Generate the BRK1900 compatible bitfile.
- Upload the bitfile to the ECM/BRK1900 using the instructions provided above in ‘Configuring a Bitfile’.