This reference is provided to help guide you through the design process of a mating peripheral to the ECM1900. It is not intended to be a comprehensive instruction manual. While we put forth great effort to reduce the effort required to build an FPGA-enabled platform, there are hundreds of pages of product documentation from Xilinx that should be considered. Use this guide as a roadmap and starting point for your design effort.
Electrical Design Guide
Input Power Supply Connection
Input power to the ECM1900 must be applied either through mezzanine header MC3. For information on the barrel jack dimensions and polarity, see Powering the ECM1900. For information on mezzanine header pin assignments, see the ECM1900 Pins Reference.
Total Power Budget
The total operating power budget is an important system consideration. The power budget for the ECM1900 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.
The onboard ECM1900 power supply regulators provide power for all on-board systems, including the user-adjustable VIO rails provided to the mezzanine headers. The Power Budget table on the Powering the ECM1900 page indicates the total current available for each supply rail. This table may be used to estimate the total amount of input power required for your design.
FPGA I/O Bank Selection and I/O Standard
Details on the available standards can be found in the following Xilinx documentation:
- Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
- UltraScale Architecture SelectIO Resources (UG571)
FPGA I/O Bank Selection and Voltage
Voltage supply rails VCCO_28, VCCO_67, VCCO_68, VCCO_87_88 power the FPGA I/O banks indicated in the supply rail net names. For information on configuring these voltages using FrontPanel, see the Device Settings page in the ECM1900 documentation. See the ECM1900 Pins Reference for details about FPGA bank power assignments.
Mechanical Design Guide
Mezzanine Connector Placement
Refer to the ECM1900 mating board diagram for placement locations of the QTH connectors, mounting holes, and jack screw standoffs. This diagram can be found on the Specifications page of the ECM1900 documentation.
Confirm the Connector Footprint
For recommended PCB layout of the QTH connector, refer to the QTH footprint drawing.
Confirm Mounting Hole Locations
Refer to the ECM1900 Specifications for a comprehensive mechanical drawing. Also refer to the BRK1900 as a reference platform. The BRK1900 design files can be found in the Downloads section of the Pins website.
Refer to the Samtec jack screw standoff instructions for information on using the jack screws to mate and unmate the ECM1900 module to the carrier board. For our version of these instructions, please visit Jack Screw Instructions.
Confirm Other Mechanical Placements
Refer to the ECM1900 mechanical drawing for locations of the two vertical-launch USB jacks. This drawing is available on the Specifications page of the ECM1900 documentation.
Thermal Dissipation Requirements
Thermal dissipation for the ECM1900 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.
An active FPGA cooling solution is recommended for any design with high power consumption. Opal Kelly provides an optional fansink designed to clip onto the ECM1900. See the Powering the ECM1900 page for more information. Some designs may require a different cooling solution. Thermal analysis and simulation may be required.
Determine the Mated Board Stacking Height
The Samtec QSH-series connectors on the ECM1900 mate with QTH-series connectors on the carrier board. The QTH series is available in several stacking height options from 5 to 25 mm. The stack height is determined by the “lead style” of the QTH connector.
Note that increased stack height can lead to decreased high-speed channel performance. Information on 3-dB insertion loss point is available at the Samtec product page link above.