The ECM1900 requires a clean, filtered, DC supply within the range of 6 V to 15 V. This supply must be delivered through the mezzanine connector MC3. Using all 10 available pins, this connection has a maximum current rating of 20 A.
The ECM1900 power distribution system is quite complex, with several supplies designed to provide suitable, efficient power for several systems and modules. A schematic diagram of the system follows, with input (+VDC) shown to the left and accessible supply rails shown to the right.
The ECM1900 is designed to be operated from a single 6-15 VDC power source supplied through mezzanine connector MC3. This provides for the several high-efficiency switching regulators on-board to provide multiple DC voltages for various components on the module as well as the user-adjustable I/O supplies.
Power Supply Monitoring
Multiple voltage, current, and temperature sensors are available on the ECM1900. Please see the I2C Peripherals documentation for details on interfacing to these devices.
VIO/VCCO I/0 Bank Associations
The VIO and VCCO naming associations and the I/O banks they power are as follows:
|VIO4||VCCO_87_88||87 & 88|
The VIO are programmable voltage step down ICs that can be programmed on the ECM1900 using the ‘set-clock-ecm1900’ application that is baked into the provided Linux Images. The sources for this application be be found at the following GitHub repository: opalkelly-opensource/ecm1900tools
These VIO voltages will need to be enabled and programmed to the desired voltage to power these I/O banks if you desire to work with any of the VCCO rails or Bank I/O, both of which are connected to the MC connectors. You will need to determine the I/O bank of the pins you require by inspecting the ECM1900 Pins page and program the necessary VIO/VCCO to the correct voltage for your design.
You can determine which I/O bank an FPGA pin is connected to from the Pins page by selecting ‘Display Options’ then ‘I/O Bank’ or you may inspect the ‘PIN DESCRIPTION’ which will have the Bank located within its name. For example ‘B68_L1P’ is connected to Bank 68.
The table below can help you determine your power budget for each supply rail on the ECM1900. All values are highly dependent on the application, speed, usage, and so on. Entries we have made are based on typical values presented in component datasheets or approximations based on Xilinx power estimator results. Shaded boxes represent unconnected rails to a particular component. Empty boxes represent data that the user must provide based on power estimates.
The user may also need to adjust parameters we have already estimated (such as FPGA Vcco values) where appropriate. All values are shown in milliwatts (mW) unless otherwise indicated.
“PL” indicates the component is related to the “programmable logic” portion of the FPGA device. “PS” indicates the component is related to the “processing system”.
|COMPONENT(S)||0.85 V||0.90 V||0.90 V||1.2 V||1.2 V||1.8 V||3.3 V||VCCO_28||VCCO_67||VCCO_68||VCCO_87_88|
|DDR4 VTT Termination||925|
|USB 2.0 PHY||55|
|PL VCCINT, VCCINT_IO, VCCBRAM|
|PS INTLP, INTFP, INTFP_DDR|
|PS VCCINT_VCU (7EV only)|
|PL VCCAUX, VCCAUX_IO||1,450|
|PL VCCO64 + VCCO65 (USB Host Interface)||25|
|PL VCCO64 + VCCO65 + VCCO66 (DDR4)||250|
|PL VCCO87 + VCCO88|
|PS VCCO_PSIO4_504 (DDR4)||810|
Example ECM1900-ZU7EG FPGA Power Consumption
Xilinx Power Estimator (XPE) version 2018.2.2 was used to compute the following power estimates for the VCCINT supply. These are simply estimates; your design requirements may vary considerably. The numbers below indicate approximately 80% utilization.
|COMPONENT||PARAMETERS||VCCINT POWER (MW)|
|Clock||300 MHz GCLK, 250,000 fanout||1,957|
|Clock||350 MHz GCLK, 150,000 fanout||1,442|
|Logic||300 MHz, 50,000 logic LUTs, 25,000 shift registers, 25,000 distributed RAMs, 250,000 registers||6,145|
|Logic||350 MHz, 40,000 logic LUTs, 150,000 registers||3,393|
|Logic||667 MHz (DDR4), 60,000 logic LUTs||3,196|
|BRAM||18-bit, 300 MHz, 250 block RAMs, 50% toggle rate||203|
|BRAM||36-bit, 350 MHz, 150 block RAMs, 50% toggle rate||284|
|DSP||500 MHz, 1500 slices, 12.5% toggle rate||3,448|
|GTH||20 channels, 16.375 Gb/s||1,004|
|Misc.||DCM, PLL, VCCINT_IO, etc.||500|
The module is designed to accept a Radian EZ Snap clip-on fansink.
|Opal Kelly Incorporated||FANSINK-35X35||Active heatsink with DC fan|
The active heat sink above includes a small fan which connects to the fan controller on-board for manual or automatic fan speed control. The fan is powered directly by the input supply to the ECM1900. The fan is specified for a nominal operating voltage of 7-13.8 VDC. Supply voltages outside of this range might be possible, but could lead to fan startup and performance issues under certain conditions. The fan is powered directly by the input supply, and therefore the maximum fan RPM is related to the external supply voltage. Designs with high FPGA on-chip power consumption must take this into account when selecting an operating voltage and heat sink.
The FANSINK-35X35 is available for purchase directly from Opal Kelly.