BRK1900 ZYNQMP Configuration
The hard processor system (PS) on the Zynq UltraScale+ requires configuration to understand how to interact with the peripherals on the BRK1900. At boot, this configuration is entered into registers on the CPU through the FSBL or U-Boot SPL. Any changes made to this configuration will require generating a new hardware handoff (hdf) file along with a re-build of the U-Boot SPL or FSBL.
The configuration parameters below correspond to the configuration for the reference design provided by Opal Kelly. Applications conforming to the settings outlined below will be compatible with the reference designs and official Linux image from Opal Kelly. Other designs may require some changes to the parameters listed below, resulting in incompatibilities with the Opal Kelly U-Boot and Linux configuration.
PS-PL Configuration
| PARAMETER | ECM1900 |
|---|---|
| General | |
| Fabric Reset Enable | Disabled |
| All other settings | Default/Disabled |
| HP Master AXI Interface | |
| AXI HPM0 LPD | Disabled |
| All other settings | Default/Disabled |
Peripheral I/O Pins
| MIO PIN (RANGE) | ASSIGNMENT |
|---|---|
| MIO 0-2 | GPIO0 |
| MIO 3 | USB1 Reset |
| MIO 4-13 | GPIO0 |
| MIO 14-15 | UART0 |
| MIO 16-17 | I2C1 |
| MIO 18-25 | GPIO0 |
| MIO 26-37 | GEM0 |
| MIO 38 | USB0 Reset |
| MIO 39-42 | SD1 |
| MIO 43-44 | GPIO1 |
| MIO 45 | SD1 Card Detect |
| MIO 46-51 | SD1 |
| MIO 52-63 | USB0 |
| MIO 64-75 | USB1 |
| MIO 76-77 | MDIO0 |
| GT Lane2 | SATA Lane0 |
| GT Lane3 | USB1 (USB 3.0) |
MIO Configuration
This majority of this section is configured correctly according to the settings entered in the Peripheral I/O Pins section.
Bank 0-3 on the ECM1900 runs at 1.8V (LVCMOS18).
The following changes should be made:
| I/O PERIPHERALS | |
|---|---|
| SD 1 | |
| CD | MIO 45 |
| USB1 | |
| USB 3.0 | Enable |
| USB Reset | Separate MIO Pin |
| USB0 | MIO 38 |
| USB1 | MIO 3 |
| GEM0 | |
| MDIO 0 | MIO 76-77 |
Clock Configuration
Input Clocks
All values can be set at default, except:
| NAME | SOURCE | INPUT FREQ(MHZ) |
|---|---|---|
| PSS_REF_CLK | PS_REF_CLK | 50 |
| SATA | Ref Clk1 | 125 |
| USB1 | Ref Clk2 | 26 |
Output Clocks
All values can be set at default, except:
| COMPONENT | CLOCK SOURCE | REQUESTED FREQUENCY (MHZ) |
|---|---|---|
| Processor/Memory Clocks | ||
| ACPU | ARM PLL (APLL) | 1200 |
| DDR | DDR PLL (DPLL) | 600 |
Interrupts
All Fabric Interrupts are disabled by default in the reference design.