ECM1900

DDR4 Memory

The ECM1900 includes two independent DDR4 memory interfaces.

PS (MPSoC): 4-GiByte, 64-bit + ECC
PL (Fabric): 4-Gibyte, 72-bit

With the -1 speed grade of the Zynq UltraScale+ device, the maximum clock rate is 1200 MHz for each interface, giving a maximum peak memory bandwidth of 154 Gibits/s per interface.

PS Memory Configuration(MPSoC)

These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on Zynq UltraScale+ MPSoc(3.3) IP and Vivado 2020.2. Everything under “DDR Configuration” can be kept at the default settings, except the following:

PARAMETER	ECM1900
Requested Device Frequency (MHz)	1200
ECC	Enabled
Speed Bin	DDR4-2400T
Cas Latency (cycles)	17
RAS to CAS Delay (cycles)	17
Precharge Time (cycles)	17
Cas Write Latency (cycles)	16
tRC (ns)	46.16
tRASmin (ns)	32.0
tFAW	30.0
DRAM IC Bus Width (per die)	16 Bits
DRAM Device Capacity (per die)	8192 MBits
Bank Group Address Count (Bits)	1
Row Address Count (Bits)	16
Other Options	Default

PL Memory (Fabric)

The DDR4 SDRAM is connected exclusively to the 1.2-V I/O on Banks 64, 65, and 66 of the FPGA. The tables below list these connections.

DDR4 PIN	FPGA PIN
RESET	AK8
CKp	AN12
CKn	AP12
CKE	AP10
CS	AG13
DQS0_t	AM21
DQS0_c	AN21
DQS1_t	AK22
DQS1_c	AK23
DQS2_t	AF23
DQS2_c	AG23
DQS3_t	AA18
DQS3_c	AB18
DQS4_t	AM14
DQS4_c	AN14
DQS5_t	AK15
DQS5_c	AK14
DQS6_t	AH14
DQS6_c	AJ14
DQS7_t	AA16
DQS7_c	AA15
DQS8_t	AC12
DQS8_c	AD12
DM0	AP19
DM1	AL20
DM2	AH22
DM3	AE18
DM4	AP18
DM5	AM16
DM6	AH18
DM7	AD15
DM8	AF11

DDR4 PIN	FPGA PIN
A0	AN11
A1	AJ10
A2	AH9
A3	AN9
A4	AP11
A5	AM9
A6	AJ11
A7	AL8
A8	AJ12
A9	AM8
A10	AL12
A11	AH12
A12	AL11
A13	AK10
A14 / WEb	AM13
A15 / CAS	AL10
A16 / RAS	AM10
BA0	AK12
BA1	AN8
BG0	AL13

DDR4 PIN	FPGA PIN	DDR4 PIN	FPGA PIN	DDR4 PIN	FPGA PIN	DDR4 PIN	FPGA PIN	DDR4 PIN	FPGA PIN
D0	AM19	D16	AG21	D32	AN13	D48	AF18	D64	AD14
D1	AN19	D17	AH21	D33	AP13	D49	AG18	D65	AE14
D2	AP21	D18	AG19	D34	AM18	D50	AE17	D66	AE13
D3	AP22	D19	AG20	D35	AN18	D51	AF17	D67	AF13
D4	AN22	D20	AF21	D36	AP16	D52	AF16	D68	AE12
D5	AP23	D21	AF22	D37	AP15	D53	AF15	D69	AF12
D6	AM23	D22	AE23	D38	AN17	D54	AG15	D70	AB13
D7	AN23	D23	AE24	D39	AN16	D55	AG14	D71	AC13
D8	AL22	D24	AB19	D40	AL16	D56	AC17
D9	AL23	D25	AC19	D41	AL15	D57	AC16
D10	AJ19	D26	AD20	D42	AK18	D58	AB16
D11	AK19	D27	AE20	D43	AL18	D59	AB15
D12	AJ20	D28	AC18	D44	AJ17	D60	AA14
D13	AK20	D29	AD19	D45	AK17	D61	AB14
D14	AJ21	D30	AA19	D46	AJ16	D62	AD17
D15	AJ22	D31	AA20	D47	AJ15	D63	AD16

MIG Settings

Zynq UltraScale+ devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. See How-To Apply DDR MIG Settings and Vivado Board File to generate Xilinx’s MIG IP Core.

For reference, we list the configuration parameters below. These parameters have been used successfully within Opal Kelly but your design needs may require deviations. All settings are based on MIG 2.2 and Vivado 2020.2. Everything can be kept at the default settings, except the following:

PARAMETER	ECM1900
Controller Type	DDR4 SDRAM
Memory Device Interface Speed(ps)	833(1200MHz)
Reference Input Clock Speed (ps)	9996(100.04Mhz)
Enable Custom Parts Data File	Enabled
Memory Part	MT40A512M16HA-075-OK (See Note below)
IO Memory Voltage	1.2V
Data Width	72
ECC	Optional (Enabled for RAMTester sample)
Cas Latency	17
Cas Write Latency	12
Advanced Clocking	Default
Advanced Options	Default

The MT40A512M16HA-075 DDR4 memory device used on the ECM1900 is not included in the MIG from Xilinx and must be added as a custom part. Download the micron_075_OK.csv file below and then select it as the “Custom Parts File” in the DDR4 SDRAM MIG IP configuration tool. ENsure that you have selected the “MT40A512M16HA-075-OK” memory part.

micron_075_OK Download