DDR4 Memory

The ECM1900 includes two independent DDR4 memory interfaces.

  • PS (MPSoC): 4-GiByte, 64-bit + ECC
  • PL (Fabric): 4-Gibyte, 72-bit

With the -1 speed grade of the Zynq UltraScale+ device, the maximum clock rate is 1200 MHz for each interface, giving a maximum peak memory bandwidth of 154 Gibits/s per interface.

PS Memory Configuration(MPSoC)

These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on Zynq UltraScale+ MPSoc(3.3) IP and Vivado 2020.2. Everything under “DDR Configuration” can be kept at the default settings, except the following:

PARAMETERECM1900
Requested Device Frequency (MHz)1200
ECCEnabled
Speed BinDDR4-2400T
Cas Latency (cycles)17
RAS to CAS Delay (cycles)17
Precharge Time (cycles)17
Cas Write Latency (cycles)16
tRC (ns)46.16
tRASmin (ns)32.0
tFAW30.0
DRAM IC Bus Width (per die)16 Bits
DRAM Device Capacity (per die)8192 MBits
Bank Group Address Count (Bits)1
Row Address Count (Bits)16
Other OptionsDefault

PL Memory (Fabric)

The DDR4 SDRAM is connected exclusively to the 1.2-V I/O on Banks 64, 65, and 66 of the FPGA. The tables below list these connections.

DDR4 PINFPGA PIN
RESETAK8
CKpAN12
CKnAP12
CKEAP10
CSAG13
DQS0_tAM21
DQS0_cAN21
DQS1_tAK22
DQS1_cAK23
DQS2_tAF23
DQS2_cAG23
DQS3_tAA18
DQS3_cAB18
DQS4_tAM14
DQS4_cAN14
DQS5_tAK15
DQS5_cAK14
DQS6_tAH14
DQS6_cAJ14
DQS7_tAA16
DQS7_cAA15
DQS8_tAC12
DQS8_cAD12
DM0AP19
DM1AL20
DM2AH22
DM3AE18
DM4AP18
DM5AM16
DM6AH18
DM7AD15
DM8AF11
DDR4 PINFPGA PIN
A0AN11
A1AJ10
A2AH9
A3AN9
A4AP11
A5AM9
A6AJ11
A7AL8
A8AJ12
A9AM8
A10AL12
A11AH12
A12AL11
A13AK10
A14 / WEbAM13
A15 / CASAL10
A16 / RASAM10
BA0AK12
BA1AN8
BG0AL13
DDR4 PINFPGA PINDDR4 PINFPGA PINDDR4 PINFPGA PINDDR4 PINFPGA PINDDR4 PINFPGA PIN
D0AM19D16AG21D32AN13D48AF18D64AD14
D1AN19D17AH21D33AP13D49AG18D65AE14
D2AP21D18AG19D34AM18D50AE17D66AE13
D3AP22D19AG20D35AN18D51AF17D67AF13
D4AN22D20AF21D36AP16D52AF16D68AE12
D5AP23D21AF22D37AP15D53AF15D69AF12
D6AM23D22AE23D38AN17D54AG15D70AB13
D7AN23D23AE24D39AN16D55AG14D71AC13
D8AL22D24AB19D40AL16D56AC17
D9AL23D25AC19D41AL15D57AC16
D10AJ19D26AD20D42AK18D58AB16
D11AK19D27AE20D43AL18D59AB15
D12AJ20D28AC18D44AJ17D60AA14
D13AK20D29AD19D45AK17D61AB14
D14AJ21D30AA19D46AJ16D62AD17
D15AJ22D31AA20D47AJ15D63AD16

MIG Settings

Zynq UltraScale+ devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on MIG 2.2 and Vivado 2020.2. Everything can be kept at the default settings, except the following:

PARAMETERECM1900
Controller TypeDDR4 SDRAM
Memory Device Interface Speed(ps)833(1200MHz)
Reference Input Clock Speed (ps)9996(100.04Mhz)
Enable Custom Parts Data FileEnabled
Memory PartMT40A512M16HA-075-OK (See Note below)
IO Memory Voltage1.2V
Data Width72
ECCOptional (Enabled for RAMTester sample)
Cas Latency17
Cas Write Latency12
Advanced ClockingDefault
Advanced OptionsDefault

The MT40A512M16HA-075 DDR4 memory device used on the ECM1900 is not included in the MIG from Xilinx and must be added as a custom part. Download the micron_075_OK.csv file below and then select it as the “Custom Parts File” in the DDR4 SDRAM MIG IP configuration tool. ENsure that you have selected the “MT40A512M16HA-075-OK” memory part.