Expansion Connectors

Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the ECM1900 may be found at the link to the right.

 

Fan Power Supply

A small 2-pin connector (Molex 53398-0271) at J4 provides power to an optional fansink for FPGA cooling. This fan is controlled by a digital fan controller as part of the Device Sensors and Device Settings capabilities. Please see the Device Settings section for details on controlling the fan.

The fansink is powered directly by the +VDCIN input voltage to the ECM1900. The allowable range for +VDCIN is 6-15 VDC. When utilizing the Opal Kelly FANSINK-35X35, it is recommended to use an input voltage within the specified operating range of the fansink: 7-13.8 VDC.

PINSIGNAL
1GND
2+VDCIN

Expansion Connectors

The ECM1900 uses three high-density Samtec connectors to provide access to signals on the module. These are precision connectors and may have a high insertion / removal force. To prevent damage to the module, PCB, connectors, and other components on the board, it is important to mate and un-mate the module from the base board carefully.

The BRK1900 includes a set of Samtec JSO jack screw standoffs to aid in assembly and disassembly of the ECM1900 to the BRK1900. We recommend similar mechanical design for any board that mates to the ECM1900.

Please visit our Jack Screw Instructions for more information.

Three high-density expansion connectors are available on the bottom side of the ECM1900: MC1 (120 pins), MC2 (120 pins), and MC3 (180 pins). These expansion connectors provide user access to several power rails on the ECM1900, the JTAG interface on the FPGA, and 248 dedicated I/O pins on the FPGA, including several global clock inputs. Twenty-four high-speed gigabit transceiver signals are also available through these expansion connectors.

The MC1 connector is Samtec part number QSH-060-01-x-D-A.  The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-060-01-x-D-A part is used on the BRK1900 breakout board. The -x indicates the plating option. See the Samtec data sheet for details.

SAMTEC PART NUMBERMATED HEIGHT
QTH-060-01-x-D-A5.00mm (0.197″)
QTH-060-02-x-D-A8.00mm (0.315″)
QTH-060-03-x-D-A11.00mm (0.433″)
QTH-060-04-x-D-A16.00mm (0.630″)
QTH-060-05-x-D-A19.00mm (0.748″)
QTH-060-07-x-D-A25.00mm (0.984″)

The MC2 connector is Samtec part number QSH-060-01-x-D-DP-A.  The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-060-01-x-D-DP-A part is used on the BRK8350 breakout board.

SAMTEC PART NUMBERMATED HEIGHT
QTH-060-01-x-D-DP-A5.00mm (0.197″)
QTH-060-02-x-D-DP-A8.00mm (0.315″)
QTH-060-03-x-D-DP-A11.00mm (0.433″)
QTH-060-04-x-D-DP-A16.00mm (0.630″)
QTH-060-05-x-D-DP-A19.00mm (0.748″)
QTH-060-07-x-D-DP-A25.00mm (0.984″)

The MC3 connector is Samtec part number QSH-090-01-x-D-A.  The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-090-01-x-D-A part is used on the BRK8350 breakout board.

SAMTEC PART NUMBERMATED HEIGHT
QTH-090-01-x-D-A5.00mm (0.197″)
QTH-090-02-x-D-A8.00mm (0.315″)
QTH-090-03-x-D-A11.00mm (0.433″)
QTH-090-04-x-D-A16.00mm (0.630″)
QTH-090-05-x-D-A19.00mm (0.748″)
QTH-090-07-x-D-A25.00mm (0.984″)

Jack Screw Standoffs

The ECM1900 uses Samtec Jack Screw Standoffs to ensure even mounting and un-mounting pressure when connecting to a base board. The table below lists the appropriate Samtec Jack Screw Standoffs along with the total mated height. The JSO-0515-01 part is used on the BRK1900 breakout board. Samtec Jack Screw Standoffs are sold as a set consisting of the base, jack screw, washer, and mounting screw. Four Jack Screw Standoffs are required to mount the ECM1900 to a base board.

SAMTEC PART NUMBERMATED HEIGHTBASE BOARD CONNECTION STYLE
JSO-0515-015.00mm (0.197″)Press fit
JSO-0815-018.00mm (0.315″)Press fit
JSO-0815-03-L8.00mm (0.315″)Threaded
JSO-1115-03-L11.00mm (0.433″)Threaded
JSO-1615-03-L16.00mm (0.630″)Threaded

Please review and follow the Jack Screw Instructions when mating and un-mating.

FPGA Bank Connections

Mezzanine connectors MC1, MC2, and MC3 are high-density connectors providing access to power, fabric I/O, transceivers, and several other signals. Pin mappings are listed on the Pins page linked above. For more details about specific FPGA inputs and outputs, see the Zynq UltraScale+ documentation.

MC1 is a 120-pin connector providing access to fabric I/O, MPSoC I/O, and MPSoC configuration signals. MC2 is a 120-pin connector with differential pair spacing. This connector provides access to the GTH and GTR transceivers on the FPGA. MC3 is a 180-pin connector providing access to fabric I/O and several on-board power supplies. The input power supply must be provided to the module through MC3.

FPGA BANKHR / HP / MIOMCXVIO (*)VREFI/O AVAILABLE
28HPMC1VCCO_28 (adjustable)VREF_2850 (including 3 GC pairs)
500MIOMC11.8V (fixed)n/a22
501MIOMC11.8V (fixed)n/a12
502MIOMC11.8V (fixed)n/a14
67HPMC2VCCO_67 (adjustable)VREF_6750 (including 3 GC pairs)
68HPMC2VCCO_68 (adjustable)VREF_6852 (including 4 GC pairs)
87HRMC2VCCO_87_88 (adjustable)n/a24 (including 4 HDGC pairs)
88HRMC2VCCO_87_88 (adjustable)n/a24 (including 4 HDGC pairs)

(*) – Refer to Device Settings for available voltage ranges on adjustable I/O supplies.

MIO = Multi-Use I/O (Processor System)

HP = High-performance I/O (Programmable Logic)

HD = High-density I/O (Programmable Logic)

Setting the Adjustable I/O Voltages

The high-efficiency switching regulators on the ECM1900 provide four adjustable bank voltages: VCCO_28, VCCO_67, VCCO_68, and VCCO_87_88. These are connected to the FPGA bank VCCO rails according to the tables above. Please see the Device Settings page for information on configuring these voltages.

For modes that read settings from an IPMI EEPROM on the peripheral, the XEM8350 expects to find this EEPROM at I2C address 0xA2.

Note: Changes to VCCO settings require a power cycle to take effect.

SYSMON

The Xilinx Zynq UltraScale+ PL SYSMON ADC input feature is routed through two 1-kΩ resistors to the MC2 connector. There is a 0.01 µF capacitor installed across the two FPGA pins for decoupling.

FPGA FUNCTIONFPGA PINMC1 PINRESISTOR REFDES
VNU1756R128
VPT1854R127

Considerations for Differential Signals

The ECM1900 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs.  Please refer to the Xilinx Zynq UltraScale+ documentation for details on using differential I/O standards with the Zynq UltraScale+ FPGA.

FPGA I/O Bank Voltages

In order to use differential I/O standards with the Zynq UltraScale+, you must set the VCCO voltages for the banks in use to the correct voltage according to the Xilinx Zynq UltraScale+ documentation.  Please see the section above entitled “Setting the Adjustable I/O Voltages” for details.

Characteristic Impedance

The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.

Differential Pair Lengths

In many cases, it is desirable that the route lengths of a differential pair be matched within some specification.  Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Differential pairs are generally matched to within 10 mils.

Reference Voltage Pins (Vref)

The Xilinx Zynq UltraScale+ supports both internal and externally-applied input voltage thresholds for some input signal standards. The ECM1900 supports these Vref applications for banks 28, 67, and 68. Please see the Xilinx Zynq UltraScale+ documentation for more details.

FPGA BANKVCCOFPGA PINMCX PIN
28VCCO_28M23MC3:162
67VCCO_67L18MC3:94
68VCCO_68J12MC3:50

I/O State at Power On

Xilinx Zynq UltraScale+ FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the ECM1900 holds the PUDC_B pin high with a 1kΩ resistor at R130, disabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 0Ω resistor at R131 and removing the 1kΩ resistor at R130, forcing the PUDC_B pin low.