|Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.|
Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.
The Pins reference for the ECM1900 may be found at the link to the right.
|ECM1900 Pins Reference|
Fan Power Supply
A small 2-pin connector (Molex 53398-0271) at J4 provides power to an optional fansink for FPGA cooling. This fan is controlled by a digital fan controller as part of the Device Sensors and Device Settings capabilities. Please see the Device Settings section for details on controlling the fan.
The fansink is powered directly by the +VDCIN input voltage to the ECM1900. The allowable range for +VDCIN is 6-15 VDC. When utilizing the Opal Kelly FANSINK-35X35, it is recommended to use an input voltage within the specified operating range of the fansink: 7-13.8 VDC.
Three high-density expansion connectors are available on the bottom side of the ECM1900: MC1 (120 pins), MC2 (120 pins), and MC3 (180 pins). These expansion connectors provide user access to several power rails on the ECM1900, the JTAG interface on the FPGA, and 248 dedicated I/O pins on the FPGA, including several global clock inputs. Twenty-four high-speed gigabit transceiver signals are also available through these expansion connectors.
The MC1 connector is Samtec part number QSH-060-01-x-D-A. The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-060-01-x-D-A part is used on the BRK1900 breakout board. The -x indicates the plating option. See the Samtec data sheet for details.
|SAMTEC PART NUMBER||MATED HEIGHT|
The MC2 connector is Samtec part number QSH-060-01-x-D-DP-A. The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-060-01-x-D-DP-A part is used on the BRK1900 breakout board.
|SAMTEC PART NUMBER||MATED HEIGHT|
The MC3 connector is Samtec part number QSH-090-01-x-D-A. The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-090-01-x-D-A part is used on the BRK1900 breakout board.
|SAMTEC PART NUMBER||MATED HEIGHT|
Jack Screw Standoffs
The ECM1900 uses Samtec Jack Screw Standoffs to ensure even mounting and un-mounting pressure when connecting to a base board. The table below lists the appropriate Samtec Jack Screw Standoffs along with the total mated height. The JSO-0515-01 part is used on the BRK1900 breakout board. Samtec Jack Screw Standoffs are sold as a set consisting of the base, jack screw, washer, and mounting screw. Four Jack Screw Standoffs are required to mount the ECM1900 to a base board.
|SAMTEC PART NUMBER||MATED HEIGHT||BASE BOARD CONNECTION STYLE|
|JSO-0515-01||5.00mm (0.197″)||Press fit|
|JSO-0815-01||8.00mm (0.315″)||Press fit|
Please review and follow the Jack Screw Instructions when mating and un-mating.
FPGA Bank Connections
Mezzanine connectors MC1, MC2, and MC3 are high-density connectors providing access to power, fabric I/O, transceivers, and several other signals. Pin mappings are listed on the ECM1900 Pins page. For more details about specific FPGA inputs and outputs, see the Zynq UltraScale+ documentation.
MC1 is a 120-pin connector providing access to fabric I/O, MPSoC I/O, and MPSoC configuration signals. MC2 is a 120-pin connector with differential pair spacing. This connector provides access to the GTH and GTR transceivers on the FPGA. MC3 is a 180-pin connector providing access to fabric I/O and several on-board power supplies. The input power supply must be provided to the module through MC3.
|FPGA BANK||HR / HP / MIO||MCX||Bank IO Level||VREF||I/O AVAILABLE|
|28||HP||MC1||VCCO_28 (adjustable)||VREF_28||50 (including 3 GC pairs)|
|67||HP||MC3||VCCO_67 (adjustable)||VREF_67||50 (including 3 GC pairs)|
|68||HP||MC3||VCCO_68 (adjustable)||VREF_68||52 (including 4 GC pairs)|
|87||HR||MC3||VCCO_87_88 (adjustable)||n/a||24 (including 4 HDGC pairs)|
|88||HR||MC3||VCCO_87_88 (adjustable)||n/a||24 (including 4 HDGC pairs)|
MIO = Multi-Use I/O (Processor System)
HP = High-performance I/O (Programmable Logic)
HD = High-density I/O (Programmable Logic)
Setting the Adjustable I/O Voltages
Four high-efficiency switching regulators onboard the ECM1900 provide the adjustable bank voltages: VCCO_28, VCCO_67, VCCO_68, and VCCO_87_88. These are connected to the FPGA bank VCCO rails according to the table above. Please see the syzygy-ecm1900 example application for information on configuring these voltages.
An external IPMI EEPROM can be placed on the peripheral to automatically configure the adjustable voltage rails. By default this EEPROM should use I2C address
1010100x and must be connected to the MC1 I2C pins.
Note: Changes to VCCO regulator settings require a power cycle to take effect.
The Xilinx Zynq UltraScale+ PL SYSMON ADC input feature is routed through two 1 kΩ resistors to the MC2 connector. There is a 0.01 µF capacitor installed across the two FPGA pins for decoupling.
|FPGA FUNCTION||FPGA PIN||MC1 PIN||RESISTOR REFDES|
Bank 503 Configuration
The Bank 503 configuration pins are brought out to the expansion connector MC1. These signals are all 1.8V and are directly connected to MC1, with some having pull resistors on board the ECM1900. The pull resistors are listed in the table below. See the Pins List for full pinout information.
For more information on boot modes see Table 11-1 in Xilinx document UG1085.
|PS_DONE||4.75 kΩ to 1.8V||R114|
|PS_INIT_B||4.75 kΩ to 1.8V||R112|
|PS_SRST_B||4.75 kΩ to 1.8V||R111|
|PS_PROG_B||4.75 kΩ to 1.8V||R113|
|POR_OVERRIDE||0 Ω to ground||R119|
|PS_MODE0||4.75 kΩ to ground||R106|
|PS_MODE1||4.75 kΩ to 1.8V||R101|
|PS_MODE2||4.75 kΩ to 1.8V||R100|
|PS_MODE3||4.75 kΩ to 1.8V||R99|
Reference Voltage Pins (Vref)
The Xilinx Zynq UltraScale+ supports both internal and externally-applied input voltage thresholds for some input signal standards. The ECM1900 supports these Vref applications for banks 28, 67, and 68. Please see the Xilinx Zynq UltraScale+ documentation for more details.
|FPGA BANK||VCCO||FPGA PIN||MCX PIN|
Considerations for Differential Signals
The ECM1900 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs. Please refer to the Xilinx Zynq UltraScale+ documentation for details on using differential I/O standards with the Zynq UltraScale+ FPGA.
FPGA I/O Bank Voltages
In order to use differential I/O standards with the Zynq UltraScale+, you must set the VCCO voltages for the banks in use to the correct voltage according to the Xilinx Zynq UltraScale+ documentation. Please see the section above entitled “Setting the Adjustable I/O Voltages” for details.
Single-ended fabric I/O are routed to the expansion connectors with 50Ω characteristic impedance. Differential fabric I/O and transceiver signals are routed to the expansion connectors as pairs with 100Ω differential impedance.
Differential Pair Lengths
In many cases, it is desirable that the route lengths of a differential pair be matched within some specification. Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Differential pairs are generally matched to within 10 mils.
I/O State at Power On
Xilinx Zynq UltraScale+ FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the ECM1900 holds the PUDC_B pin high with a 1kΩ resistor at R130, disabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 0Ω resistor at R131 and removing the 1kΩ resistor at R130, forcing the PUDC_B pin low.