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• Remove SATA lane polarity swap in setclk-reboot-init application.
• Add Support for DP83867IRPAP PHY in device tree.
• Add SYZYGY Port G to syzygy-ecm1900 application.
• Set default pulldown on MIO pin 44 for Si5341 OEb pin.
• Replace VIO# rails with VCCO names and simplify VADJ regulator function in syzygy-ecm1900 application.
• Update the ClockBuilder Pro projects for SI5341 and SI5338, and regenerate the header files for the set-clock-brk1900 and set-clock-ecm1900 applications. This update is necessary to enable the use of QSFP1 and QSFP2 in Ethernet applications.
  • Updated SI5341 settings on the ECM1900:
    • Output 7: 156.25 MHz
    • Output 8: 156.25 MHz
  • Updated SI5338 settings on the BRK1900:
    • Output 2: 156.25 MHz
    • Output 3: 156.25 MHz

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• Add “stop” key sequence to u-boot STOP
• Add device-sensors py app to image
• Add Si5341 Clk Gen bug fix

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• Initial Creation
• Sources and prebuilt image use PetaLinux 2021.2
• Imported hardware description of Zynq MPSoC from Vivado 2021.2