BRK1900 Peripherals

Several peripherals on the ECM1900 serve to implement a complete system with the ECM1900.

Peripheral Bank Connections

The table below summarizes the various connectors on the BRK1900. The ECM1900 Pin List has connection information in the “BRK1900” column. Additionally, please refer to the schematics and layout available online for detailed connection diagrams.

CONNECTOR TYPEFPGA BANK
SYZYGY Standard Port A87-88
SYZYGY Standard Port B68
SYZYGY Standard Port C67
SYZYGY Standard Port D28
SYZYGY Transceiver (TXR-4)  Port E67, GTH 225
SYZYGY Transceiver (TXR-4) Port F28, GTH 224
QSFP #187, GTH 227
QSFP #287, GTH 226
FPXGTH 223
USB 3502, GTR 505
Ethernet500, 501, 502
SATAGTR 505
2mm Breakout500, 68

Si5338 Programmable Clock

Note: This clock oscillator is separate and not synchronous to the clock provided by the USB host interface.

An Si5338B programmable oscillator provides four independent LVDS clock pairs to the PS and PL of the MPSoC. All four are connected to transceiver reference clock inputs. The input reference for the Si5338B is a fixed-frequency 25-MHz crystal oscillator. The output frequency of each channel has a range of 0.16-350 MHz. See the Si5338B data sheet for more information on configuring this part.

The Si5338Config project (see the Samples folder provided in the FrontPanel SDK) provides a simple sample design that can interface between FrontPanel and the Si5338B I2C interface. The accompanying XFP and Lua script can be used to configure the Si5338B clock generator with CSV settings generated using the Silicon Labs ClockBuilder Pro application.

The attachment below is the ClockBuilder Pro project file used to configure the Si5338B on the BRK1900 at the factory. It includes all of the configuration settings that were used to generate the CSV files in the Si5338Config project. You can use this ClockBuilder Pro project as a template for creating your own CSV configuration files. 

Transceiver Reference

SI5338B OUTPUTFPGA PIN
CLK0A (LVDS +)P27 (PS_MGTREFCLK1P_505)
CLK0B (LVDS -)P28 (PS_MGTREFCLK1N_505)
CLK1A (LVDS +)M27 (PS_MGTREFCLK2P_505)
CLK1B (LVDS -)M28 (PS_MGTREFCLK2N_505)
CLK2A (LVDS +)U10 (PL_MGTREFCLK1P_226)
CLK2B (LVDS -)U9 (PL_MGTREFCLK1N_226)
CLK3A (LVDS +)AC10 (PL_MGTREFCLK1P_223)
CLK3B (LVDS -)AC9 (PL_MGTREFCLK1N_223)

Configuration Interface

SI5338BFPGA PIN
SCLA28 (PS_MIO16)
SDAC29 (PS_MIO17)
I2C Address0b1110000

Ethernet PHY

There is a MicroChip KSZ9031RNXCA Ethernet PHY onboard the BRK1900. It supports the RGMII and MDC/MDIO user interface as well as 10Base-T, 100Base-TX, and 1000Base-T standards. The PHY is connected to the hard processor system (PS) on the Zynq 7 at the MIO pin locations listed under BRK1900 ZYNQMP Configuration. The processor system will control this PHY directly. If you would like to access this PHY from the PL, you can setup the PL to master an AXI master-slave communication link with the PS MAC core. Further information regarding this arrangement can be found within Xilinx documentation.

QSFP Transceiver Cages

The BRK1900 has two QSFP cages installed, but the optical transceivers are optional. The following ethernet fiber optic transceiver is one option.

MANUFACTURERPART NUMBERMOUSER P/NAPPROXIMATE COST
FormericaTQS-Q14H9-J83216-TQS-Q14H9-J83$212.80 / each

I2C Peripherals

Several I2C devices add functionality to the BRK1900 to help implement a complete system. These are summarized in the table below:

PART NUMBERDESIGNATORI2C ADDRESSFUNCTION 
Microchip 24AA025E48-I/SNU151010111Ethernet MAC ID PROM
Microchip 24FC256-I/SNU11010100Miscellaneous EEPROM (256 KB)
Microchip 24FC256-I/SNU3N/AFrontPanel DNA EEPROM (256 KB)
Texas Instruments HD3SS3220RNHU141100111USB Type-C controller with MUX
Texas Instruments TPS65400RGZU1911010014-channel switching regulator for SYZYGY SmartVIO

FrontPanel FPX1301 Socket

Not available at this time.

SYZYGY Ports

The SYZYGY ports onboard the BRK1900 are set to having the following I2C addresses.

For more information about SYZYGY, please SYZYGYFPGA.io.

DEVICEI2C ADDRESS
SYZYGY Port A0110000
SYZYGY Port B0110001
SYZYGY Port C0110010
SYZYGY Port D0110011
SYZYGY Port E0110100
SYZYGY Port F0110101

DisplayPort

Not currently supported with BRK1900 revision AXX.