Several peripherals on the ECM1900 serve to implement a complete system with the ECM1900.
Peripheral Bank Connections
The table below summarizes the various connectors on the BRK1900. The ECM1900 Pin List has connection information in the “BRK1900” column. Additionally, please refer to the schematics and layout available online for detailed connection diagrams.
|CONNECTOR TYPE||FPGA BANK|
|SYZYGY Standard Port A||87-88|
|SYZYGY Standard Port B||68|
|SYZYGY Standard Port C||67|
|SYZYGY Standard Port D||28|
|SYZYGY Transceiver (TXR-4) Port E||67, GTH 225|
|SYZYGY Transceiver (TXR-4) Port F||28, GTH 224|
|QSFP #1||87, GTH 227|
|QSFP #2||87, GTH 226|
|USB 3||502, GTR 505|
|Ethernet||500, 501, 502|
|2mm Breakout||500, 68|
Si5338 Programmable Clock
Note: This clock oscillator is separate and not synchronous to the clock provided by the USB host interface.
An Si5338B programmable oscillator provides four independent LVDS clock pairs to the PS and PL of the MPSoC. All four are connected to transceiver reference clock inputs. The input reference for the Si5338B is a fixed-frequency 25-MHz crystal oscillator. The output frequency of each channel has a range of 0.16-350 MHz. See the Si5338B data sheet for more information on configuring this part.
The default frequencies used in the set-clock-brk1900 application are shown below. This application is baked into the provided BRK1900 Linux image. This application is automatically run during boot in the setclk-reboot-init initializer script. The Clock Builder Pro project file used to generate the configuration data is located on GitHub. You can use this ClockBuilder Pro project as a template for creating your own configuration files. You can follow the instructions at BRK1900 Linux Image to configure any desired default frequency available after boot.
|SI5338B OUTPUT||DEFAULT FREQUENCY|
|SI5338B OUTPUT||FPGA PIN||FPGA PIN NAME|
|CLK0A (LVDS +)||P27||PS_MGTREFCLK1P_505|
|CLK0B (LVDS -)||P28||PS_MGTREFCLK1N_505|
|CLK1A (LVDS +)||M27||PS_MGTREFCLK2P_505|
|CLK1B (LVDS -)||M28||PS_MGTREFCLK2N_505|
|CLK2A (LVDS +)||U10||PL_MGTREFCLK1P_226|
|CLK2B (LVDS -)||U9||PL_MGTREFCLK1N_226|
|CLK3A (LVDS +)||AC10||PL_MGTREFCLK1P_223|
|CLK3B (LVDS -)||AC9||PL_MGTREFCLK1N_223|
There is a MicroChip KSZ9031RNXCA Ethernet PHY onboard the BRK1900. It supports the RGMII and MDC/MDIO user interface as well as 10Base-T, 100Base-TX, and 1000Base-T standards. The PHY is connected to the hard processor system (PS) on the Zynq UltraScale+ at the MIO pin locations listed under BRK1900 ZYNQMP Configuration. The processor system will control this PHY directly. If you would like to access this PHY from the PL, you can setup the PL to master an AXI master-slave communication link with the PS MAC core. Further information regarding this arrangement can be found within Xilinx documentation.
QSFP Transceiver Cages
The BRK1900 has two QSFP cages installed, but the optical transceivers are optional. The following ethernet fiber optic transceiver is one option.
|MANUFACTURER||PART NUMBER||MOUSER P/N||APPROXIMATE COST|
|Formerica||TQS-Q14H9-J83||216-TQS-Q14H9-J83||$212.80 / each|
Several I2C devices add functionality to the BRK1900 to help implement a complete system. These are summarized in the table below:
|PART NUMBER||DESIGNATOR||I2C ADDRESS||FUNCTION|
|Microchip 24AA025E48-I/SN||U15||Ethernet MAC ID PROM|
|Microchip 24FC256-I/SN||U1||Miscellaneous EEPROM (256 KB)|
|Microchip 24FC256-I/SN||U3||N/A||FrontPanel DNA EEPROM (256 KB)|
|Texas Instruments HD3SS3220RNH||U14||USB Type-C controller with MUX|
|Texas Instruments TPS65400RGZ||U19||4-channel switching regulator for SYZYGY SmartVIO|
FrontPanel FPX1301 Socket
Not available at this time.
The SYZYGY ports onboard the BRK1900 are set to having the following I2C addresses.
For more information about SYZYGY, please SYZYGYFPGA.io.
|SYZYGY Port A|
|SYZYGY Port B|
|SYZYGY Port C|
|SYZYGY Port D|
|SYZYGY Port E|
|SYZYGY Port F|
Not currently supported with BRK1900 revision AXX.