The BRK1900 is a complete reference platform for the ECM1900 Edge Compute Module™ providing multiple interfaces to various connections on the ECM1900 such as DC power input, 7x SYZYGY connectors, QSFP receptacles, a SATA connector, JTAG, ethernet PHY, USB PHY, and a programmable clock oscillator. Three additional 2mm headers provide connections to the remaining FPGA and CPU I/O pins for general purpose application.

The BRK1900 requires a clean, filtered, DC supply within the range of 6 V to 15 V. This supply is passed directly to the ECM1900 as well as being used for onboard regulators. It may be delivered in one of two ways:

1. 6-pin Mini-Fin connector – Pins 1, 2, and 3 are tied to the input supply net +VDCIN. Pins 4, 5, and 6 are tied to ground. The total maximum current allowed over this connector is 8 A. The part number is Molex 0455580003. The mating plug part number is Molex 0455590002. Several options for crimping pins are available, including Molex 0039000038. While it is possible to provide power using a commercial PC power supply with compatible pinout, it is recommended to create a custom cable harness for use with an appropriate bench supply.
2. DC barrel jack – The jack is part number PJ-102AH from CUI, Inc. It is a standard “canon-style” 2.1mm / 5.5mm jack. The total maximum current allowed over this connector is 5 A. The outer ring is connected to DGND. The center pin is connected to +VDCIN.

Please refer to Powering the ECM1900 for information on the ECM1900 power systems.

The BRK1900 includes two LED indicators for power status.

The ECM1900 Pin List has full connection information in the “BRK1900” columns. Additionally, please refer to the schematics and layout available on the Pins downloads page for detailed connection diagrams.

The table below summarizes the various connectors on the BRK1900. The ECM1900 Pin List has connection information in the “BRK1900” column. Additionally, please refer to the schematics and layout available online for detailed connection diagrams.

For information on the SYZYGY ports see the BRK1900 SYZYGY Ports page.

The Ethernet PHY onboard the BRK1900 supports the RGMII and MDC/MDIO user interface as well as 10Base-T, 100Base-TX, and 1000Base-T standards. It is connected to the hard processor system (PS) on the Zynq UltraScale+ at the MIO pin locations listed under BRK1900 ZYNQMP Configuration. The processor system will control this PHY directly. If you would like to access this PHY from the PL, you can set up the PL to master an AXI master-slave communication link with the PS MAC core. Further information regarding this arrangement can be found within Xilinx documentation.

The BRK1900 has two QSFP cages installed, but require transceivers to be used. The following Ethernet fiber optic transceiver is one option.

The Processing System (PS) side DisplayPort is connected to lanes 0-1 of the GTR transceivers. The AUX channel and the hot plug detect channel are to be connected through EMIO. The connection locations for these signals are given below:

The Processing System (PS) side DisplayPort is only supported with BRK1900 revision BXX and newer. It is not supported on revision AXX.

The BRK1900 includes a USB 3.0 host port using a Type-C connector. The USB SuperSpeed lanes are connected to one set of the PS 505 transceiver lanes. The USB 2.0 connection is provided by a Microchip USB3320C-EZK PHY connected to PS 502 MIO pins. Port current output is limited by a Diodes Incorporated AP22653AW6-7 current limiter. See the BRK1900 schematic for more connection details.

Several I2C devices add functionality to the BRK1900 to help implement a complete system. These are summarized in the table below:

Otherwise unused I/O are broken out into banks of 2mm headers. The headers pins are unpopulated by default.

For full I/O connection details see the ECM1900 Pin List.

The expansion header J4 includes the PSCONFIG signals. A 2mm male header is included to connect to the signals and to place jumpers to set the PS boot mode. For more information see AMD’s Zynq UltraScale+ TRM. Table 11‐1: Boot Modes lists the boot mode options for the PSMODE pins.

The BRK1900 (revision BXX+) has a built in USB JTAG adapter. Connect to the USB-C connector J21 for AMD tools compatible access to the ECM1900’s JTAG interface.

The JTAG connections are also wired to a dedicated 2mm header J2 that can be used with a compatible JTAG cable. The JTAG interface presented is at a 1.8V signaling voltage. This header is not populated by default. This footprint is compatible with the Molex part 87831-1420.

This clock oscillator is separate and not synchronous to the clock provided by the USB host interface.

An Si5338B programmable oscillator provides four independent LVDS clock pairs to the PS and PL of the MPSoC. All four are connected to transceiver reference clock inputs. The input reference for the Si5338B is a fixed-frequency 25-MHz crystal oscillator. The output frequency of each channel has a range of 0.16-350 MHz. See the Si5338B data sheet for more information on configuring this part.

The default frequencies used in the set-clock-brk1900 application are shown below. This application is baked into the provided BRK1900 Linux image. This application is automatically run during boot in the setclk-reboot-init initializer script. The Clock Builder Pro project file used to generate the configuration data is located on GitHub. You can use this ClockBuilder Pro project as a template for creating your own configuration files.  You can follow the instructions at BRK1900 Linux Image to configure any desired default frequency available after boot.

The ECM1900 is not hot pluggable. Disconnect all power before mounting or unmounting the ECM1900 .

The ECM1900 uses multiple high pin count expansion connectors. Care must be taken when mounting and unmounting from the BRK1900. See the Jack Screw Instructions page for the proper mounting procedure.

The BRK1900 schematics and design files are available in the Downloads section of the Pins website.

3D Models are available in SolidWorks, STEP, EASM and IGES formats.