Access to 28 high-speed serial transceiver pairs (28 Rx and 28 Tx) corresponding to GTH quads 126, 127, 128, 224, 225, 226, and 227 on the FPGA are available on the expansion connectors. MGTREFCLK1 of quad 127, MGTREFCLK0 of quad 128, MGTREFCLK1 of quad 225 and MGTREFCLK0 of quad 226 are also routed to expansion connectors. MGTREFCLK0 of quad 127 and MGTREFCLK0 of quad 225 are connected to the on-board Si5338 programmable clock.

0.1μF AC-coupling capacitors are installed between the expansion connectors and the FPGA for all MGTREFCLK signals.

AC-coupling capacitors are not installed for any of the GTH transmit or receive pairs. If AC-coupling is desired or required for the serial application, they should be installed on the peripheral side (your board).

Xilinx provides the IBERT tool to test and experiment with gigabit transceivers.  The settings below are compatible with the XEM8350 using Vivado 2019.1:

Xilinx’s IBERT tool enables an automated self-measurement of a GTH channel’s eye diagram when used in a loopback mode. Eye diagrams for two different speeds were captured using this tool with a simple loopback peripheral attached to the expansion headers. While results may vary, these are typical captures and actually represent the worst case capture over all channels for the respective rates.

Note that in loopback modes, it can be helpful to disable the GBT DFE (decision feedback equalizer) to avoid over-compensation. The TX Diff Swing must also be set so that it does not over saturate the receiver.

Measurement taken with DFE disabled, TX Diff Swing set to 600mV.

Measurement taken with DFE enabled, TX Diff Swing set to 320mV and RXTERM set to 260mV.