Clock Oscillators
Note: This clock oscillator is separate and not synchronous to the clock provided by the USB host interface.
An Si5338B programmable oscillator provides four independent LVDS clock pairs to the FPGA. Two are connected to fabric for general reference, and two are connected to transceiver reference clock inputs. The input reference for the Si5338B is a fixed-frequency 25-MHz crystal oscillator. A second oscillator footprint provides the option for an additional clock reference input to the Si5338B. The output frequency of each channel has a range of 0.16-350 MHz. See the Si5338B data sheet for more information on configuring this part.
The Si5338Config project (see the Samples folder provided in the FrontPanel SDK) provides a simple sample design that can interface between FrontPanel and the Si5338B I2C interface. The accompanying XFP and Lua script can be used to configure the Si5338B clock generator with CSV settings generated using the Silicon Labs ClockBuilder Pro application.
The GitHub link below is the ClockBuilder Pro project file used to configure the Si5338B on the XEM8350 at the factory. It includes all of the configuration settings that were used to generate the CSV files in the Si5338Config project. You can use this ClockBuilder Pro project as a template for creating your own CSV configuration files.
Default Clock Settings
| CLOCK OUTPUT | FREQUENCY |
|---|---|
| CLK0 | 100 MHz |
| CLK1 | 100 MHz |
| CLK2 | 152.3 MHz |
| CLK3 | 200 MHz |
General (Fabric) Reference
| SI5338B OUTPUT | FPGA PIN |
|---|---|
| CLK2A (LVDS +) | J23 |
| CLK2B (LVDS -) | J24 |
| CLK3A (LVDS +) | AM22 |
| CLK3B (LVDS -) | AN22 |
Transceiver Reference
| SI5338B OUTPUT | FPGA PIN |
|---|---|
| CLK0A (LVDS +) | Y32 (MGTREFCLK0P_127) |
| CLK0B (LVDS -) | Y33 (MGTREFCLK0N_127) |
| CLK1A (LVDS +) | AM10 (MGTREFCLK0P_225) |
| CLK1B (LVDS -) | AM9 (MGTREFCLK0N_225) |
Configuration Interface
| SI5338B | FPGA PIN |
|---|---|
| SCL | AJ14 |
| SDA | AJ15 |
| INTR | AK15 |
| I2C Address | 1110 000x |