The SZG-PCIEX4 routes the PCIe connector pinout to the SYZYGY Samtec connector. This module is an excellent choice for adding PCIe connectivity to your SYZYGY carrier board. The provided Samtec cable is used to connect the SZG-PCIEX4 to your host PC.

• Aligni PLM – See the Attachments tab for schematics
• SYZYGY Specification
• SYZYGY GitHub Site – Several projects that could be helpful
• SZG-PCIEX4 Reference Design
• Product Page

A TXR4 SYZYGY ports contain 4 RX/TX lanes connected to a transceiver quad of the FPGA. The SZG-PCIEX4 is a TXR4 (4-lane) peripheral and is compatible with the TXR4 carriers such as the XEM8320, BRK8350, and BRK1900. The PCIe lanes and transceiver quad’s lanes have a same order connection i.e. a 0->0, 1->1, 2->2, 3->3 lane connection. TX lanes are equipt with 0.1-uF coupling capacitors.

Through internal testing we were able to establish and exercise PCIe Gen 3 x4 Lane links up to 8 feet in cable length. Cable lengths beyond this will either fail to enumerate or train down to lower performance. Performance may vary depending on system hardware and configuration.

When using Vivado’s PCIe IPs (XDMA, QDMA, and Integrated Block) you must constrain the PCIe lanes manually to the transceiver bank’s lanes. Within the IP Wizard it is recommended to select Mode “Advanced”, then the “GT Settings” tab will become available. Within the “GT Settings” tab select “true” for “Disable GT Channel LOC Constraint. This will ensure there are no BEL constraint conflicts with these lanes and the manual constraints. Please see the SZG-PCIEX4 Reference Design for a guide on correctly constraining these lanes for your product.

The Vivado PCIe IPs provide XDC files as part of their generated output products which constrain the LOC of the transceiver bank’s lanes to the PCIe lanes as specified in Appendix B of PG213: “PCIe lane 0 is placed in the topmost GT of the top-most GT Quad by default. Subsequent lanes use the next available GTs moving vertically down the device as the lane number increments.” This results in automated LOC constraints for the PCIe’s lanes and transceiver bank’s lanes having the following connections: 0->3, 1->2, 2->1, 3->0. The SZG-PCIeX4 connected to your device through the TXR4 port will have a 0->0, 1->1, 2->2, 3->3 lane connection and is incompatible for automated pin constraints through Xilinx IPs.

At the application of power, Opal Kelly’s SmartVIO controller used on Opal Kelly SYZYGY carrier boards enable VIO power supplies later than the required 100ms PCIe standard’s requirement. VIO powers the I/O banks that PCIe PERST ultimately routes to. If the host system requiring enumeration is powering the Opal Kelly SYZYGY carrier board, PERST will not become available under 100ms from the time the host’s power rails become active. 

If you’d like the host to power your Opal Kelly SYZYGY carrier board you’ll be required to perform a warm restart of the system to successfully enumerate your PCIe endpoint. A warm restart is a reboot of your host without the removal and reapplication of power.

Alternatively, you can externally power your Opal Kelly SYZYGY carrier board and power on the host after VIO becomes active to achieve a successful enumeration.

A companion card board file is available for this SYZYGY peripheral. This companion card board file is only compatible with TXR4 ports on the SYZYGY carrier board’s board file.

Version 1.0 provides the following components:

• PCIe X4 interface
• PERST

Follow the appropriate installation instructions at Vivado Board Files.

• The SZG-PCIEX4 Companion Card does not automatically constrain the pins for the PCIe X4 Interface to the Xilinx IPs. You must manually constrain these pins through a top level .xdc constraints file or through the GUI. Please see the SZG-PCIEX4 Reference Design for an example of manually constraining these pins on the XEM8320. See “Vivado IP Constraint Automation” under “Notes and Limitations” below for more information regarding the reason for manual constraints.

• PCIe RefClk, which comes from the SZG-PCIEX4 peripheral, needs to be added into your project and connected to your Xilinx PCIe IP. The PCIe RefClk is not currently supported on the board file at this time

^{1 – VIO range may be effected by PCN-20240307}

^{2 – LVDS flag may be effected by PCN-20240307}

The source of the following pinout information is the SZG-PCIEX4 schematic. This pinout follows the SYZYGY specification for TXR4 ports.

• Column PIN NUM (J1) lists the pin number on the SYZYGY specification’s transceiver Samtec connector, this is reference designator J1 in the schematic.
• Column SIGNAL NAME lists the SYZYGY specification’s name for this pin’s connection.
• Column SCHEMATIC NET lists the net name found in the SZG-PCIEX4’s schematic for the connection.